IS42S32800D-6BL ISSI, Integrated Silicon Solution Inc, IS42S32800D-6BL Datasheet - Page 26

• Manufacturer Part Number: IS42S32800D-6BL
• Description: IC SDRAM 256MBIT 166MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32800D-6BL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-BGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 13b
• Access Time (max): 6.5/5.4ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

to a bank within the SDRAM, a row in that bank must be
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a t
to 3. This is reflected in the following example, which cov-
ers any case where 2 < [t
IS42S32800D, IS45S32800D
CHIP OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated
(see Activating Specific Row Within Specific Bank).
After opening a row (issuing an ACTIVE command), a READ
or WRITE command may be issued to that row, subject to
the t
the clock period and rounded up to the next whole number
125 MHz clock (8ns period) results in 2.25 clocks, rounded
procedure is used to convert other specification limits from
time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by t
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead.The minimum
time interval between successive ACTIVE commands to
different banks is defined by t
EXAMPLE: MEETING T
26
rcd
specification. Minimum t
COMMAND
rcd
rc
rcd
.
RCD
specification of 18ns with a
rrd
CLK
(MIN)/t
rcd
.
(MIN) WHEN 2 < [T
should be divided by
ck
ACTIVE
] ≤ 3. (The same
T0
t
NOP
RCD
T1
RCD
ACTIVATING SPECIFIC ROW WITHIN SPE-
CIFIC BANK
(MIN)/TCK] ≤ 3
BA0, BA1
A0-A11
NOP
T2
CKE
RAS
CAS
CLK
WE
CS
HIGH
READ or
WRITE
T3
DON'T CARE
Integrated Silicon Solution, Inc. - www.issi.com
BANK ADDRESS
ROW ADDRESS
T4
12/01/09
Rev. C