M25PE80-VMP6TG NUMONYX, M25PE80-VMP6TG Datasheet - Page 21

• Manufacturer Part Number: M25PE80-VMP6TG
• Description: IC FLASH 8MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PE80-VMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PE80-VMP6TG; M25PE80-VMP6TGTR

M25PE80
6.1
Table 6.
1. Instruction available only in the T9HX process (see
Write enable (WREN)
The write enable (WREN) instruction
The write enable latch (WEL) bit must be set prior to every page write (PW), page program
(PP), page erase (PE), sector erase (SE), bulk erase (BE) and write to lock register (WRLR)
instructions.
The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
FAST_READ
Instruction
WRSR
WREN
WRLR
SSE
RDSR
RDLR
READ
WRDI
RDID
RDP
PW
PP
PE
SE
BE
DP
(1)
(1)
Instruction set
Write enable
Write disable
Read identification
Read status register
Write to lock register
Write status register
Read lock register
Read data bytes
Read data bytes at higher
speed
Page write
Page program
Page erase
Subsector erase
Sector erase
Bulk erase
Deep power-down
Release from deep
power-down
Description
(Figure
One-byte instruction
0000 0110
0000 0100
1001 1111
0000 0101
1110 0101
0000 0001
1110 1000
0000 0011
0000 1011
0000 1010
0000 0010
1101 1011
0010 0000
1101 1000
1100 0111
1011 1001
1010 1011
Important note on page
7) sets the write enable latch (WEL) bit.
code
DBh
E5h
0Ah
D8h
C7h
B9h
ABh
06h
04h
9Fh
05h
01h
E8h
03h
0Bh
20h
02h
Address
bytes
6).
0
0
0
0
3
0
3
3
3
3
3
3
3
3
0
0
0
Dummy
bytes
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Instructions
1 to 256
1 to 256
1 to ∞
1 to ∞
bytes
1 to ∞
1 to 3
Data
0
0
1
1
1
0
0
0
0
0
0
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