NAND01GR3B2CZA6E NUMONYX, NAND01GR3B2CZA6E Datasheet - Page 29

• Manufacturer Part Number: NAND01GR3B2CZA6E
• Description: IC FLASH 1GBIT 63VFBGA
• Manufacturer: NUMONYX

Specifications of NAND01GR3B2CZA6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 1G (128M x 8)
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 63-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

NAND01G-B2B, NAND02G-B2C
6.5
Figure 13. Cache program operation
1. Up to 64 pages can be programmed in one cache program operation.
2. t
I/O
RB
+ Last page data loading time).
CACHEPG
Program
Page
Code
80h
Address
Inputs
is the program time for the last page + the program time for the (last − 1)
Cache program
The cache program operation is used to improve the programming throughput by
programming data using the cache register. The cache program operation can only be used
within one block. The cache register allows new data to be input while the previous data that
was transferred to the page buffer is programmed into the memory array.
The following sequence is required to issue a cache program operation (refer to
1.
2.
3.
4.
Once the program operation has started the status register can be read using the Read
Status Register command. During cache program operations SR5 can be read to find out
whether the internal programming is ongoing (SR5 = ‘0’) or has completed (SR5 = ‘1’) while
SR6 indicates whether the cache register is ready to accept new data. If any errors have
been detected on the previous page (page N-1), the cache program error bit SR1 will be set
to ‘1', while if the error has been detected on page N the error bit SR0 will be set to '1’.
When the next page (page N) of data is input with the Cache Program command, t
affected by the pending internal programming. The data will only be transferred from the
cache register to the page buffer when the pending program cycle is finished and the page
buffer is available.
If the system monitors the progress of the operation using only the Ready/Busy signal, the
last page of data must be programmed with the Page Program Confirm command (10h).
If the Cache Program Confirm command (15h) is used instead, status register bit SR5 must
be polled to find out if the last programming is finished before starting any other operations.
First Page
First of all the program setup command is issued: one bus cycle to issue the program
setup command then 4 or 5 bus write cycles to input the address (see
Table
cache register
One bus cycle is required to issue the confirm command to start the P/E/R controller
The P/E/R controller then transfers the data to the page buffer. During this the device is
busy for a time of t
Once the data is loaded into the page buffer the P/E/R controller programs the data into
the memory array. As soon as the cache registers are empty (after t
Cache Program command can be issued, while the internal programming is still
executing.
Inputs
(Cache Busy time)
Data
tBLBH5
Program
7). The data is then input (up to 2112 bytes/1056 words) and loaded into the
Cache
Code
15h
Busy
Program
Code
Page
80h
(can be repeated up to 63 times)
BLBH5
Address
Inputs
Second Page
Inputs
Data
Cache Program
Confirm Code
tBLBH5
15h
Busy
80h
th
page − (Program command cycle time
Address
Inputs
Last Page
tCACHEPG
Inputs
Data
Confirm Code
Program
Page
Device operations
BLBH5
10h
Busy
Table 6
) a new
Read Status
Figure
70h
Register
BLBH5
and
ai08672
SR0
29/61
13):
is