CY7C131-55NXC Cypress Semiconductor Corp, CY7C131-55NXC Datasheet - Page 9

• Manufacturer Part Number: CY7C131-55NXC
• Description: IC SRAM 8KBIT 55NS 52-QFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C131-55NXC

• Memory Size: 8K (1K x 8)
• Package / Case: 52-QFP
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 55 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 110 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 5 V
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2111; CY7C131-55NXC

Switching Characteristics
Over the Operating Range
Document Number: 38-06002 Rev. *G
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
23. See the last page of this specification for Group A subgroup testing information.
24. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified
25. AC Test Conditions use V
26. This parameter is guaranteed but not tested.
27. At any given temperature and voltage condition for any given device, t
28. t
29. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
Read Cycle
Write Cycle
Parameter
I
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
OL
LZCE
/I
OH,
, t
LZWE
and 30 pF load capacitance.
, t
[29]
HZOE
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power-up
CE HIGH to power-down
Write cycle time
CE LOW to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
R/W pulse width
Data set-up to write end
Data hold from write end
R/W LOW to high Z
R/W HIGH to low Z
, t
LZOE
, t
OH
HZCE
[23, 24]
= 1.6 V and V
and t
HZWE
[26, 27, 28]
[26, 27, 28]
Description
[28]
[28]
[26, 27, 28]
[26, 27, 28]
[25]
[26]
OL
[25]
[25]
are tested with C
= 1.4 V.
[26]
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
HZCE
is less than t
Min
35
35
30
30
25
15
–
0
–
–
3
–
5
–
0
–
2
0
0
–
0
7C130-35
7C131-35
7C140-35
7C141-35
LZCE
Max
and t
35
35
20
20
20
35
20
–
–
–
–
–
–
–
–
–
–
–
–
–
–
HZOE
is less than t
Min
45
45
35
35
30
20
7C130-45
7C131-45
7C140-45
7C141-45
–
0
–
–
3
–
5
–
0
–
2
0
0
–
0
LZOE
Max
45
45
25
20
20
35
20
CY7C130, CY7C130A
CY7C131, CY7C131A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
.
Min
55
55
40
40
30
20
7C130-55
7C131-55
7C140-55
7C141-55
–
0
–
–
3
–
5
–
0
–
2
0
0
–
0
Max
55
55
25
25
25
35
25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 9 of 22
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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