PSD4235G2-90UI STMicroelectronics, PSD4235G2-90UI Datasheet - Page 86

• Manufacturer Part Number: PSD4235G2-90UI
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1969

I/O ports
20.11
20.12
20.13
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Port Configuration registers (PCR)
Each Port has a set of Port Configuration registers (PCR) used for configuration. The
contents of the registers can be accessed by the MCU through normal READ/WRITE bus
cycles at the addresses given in
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, bit 0 in a register refers to bit 0 of its port. The three Port
Configuration registers (PCR), shown in
configurations. The default Power-up state for each register in
Control register
Any bit reset to ’0’ in the Control register sets the corresponding port pin to MCU I/O mode,
and a ’1’ sets it to Address Out mode. The default mode is MCU I/O. Only Ports E, F and G
have an associated Control register.
Table 42.
1. See
Direction register
The Direction register controls the direction of data flow in the I/O Ports. Any bit set to ’1’ in
the Direction register causes the corresponding pin to be an output, and any bit set to ’0’
causes it to be an input. The default mode for all port pins is input.
Figure 28
respectively. The direction of data flow for Ports A, B, C and F are controlled not only by the
direction register, but also by the output enable product term from the PLD AND Array. If the
output enable product term is not active, the Direction register has sole control of a given
pin’s direction.
An example of a configuration for a Port with the three least significant bits set to output and
the remainder set to input is shown in
Direction register for Port D has only the four least significant bits active.
Drive Select register
The Drive Select register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should be
used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select register is
set to a '1.' The default pin drive is CMOS.
Control
Direction
Drive Select
Table 46
Register name
and
(1)
Port Configuration registers (PCR)
for Drive register bit definition.
Figure 30
show the Port Architecture diagrams for Ports A/B/C and E/F/G,
E, F, G
A, B, C, D, E, F, G
A, B, C, D, E, F, G
Table
Table
6. The addresses in
Table
45. Since Port D only contains four pins, the
Port
42, are used for setting the Port
Table 6
Table 42
WRITE/READ
WRITE/READ
WRITE/READ
are the offsets in
is 00h.
MCU access
PSD4235G2