AT45DB161D-SU Atmel, AT45DB161D-SU Datasheet - Page 10

• Manufacturer Part Number: AT45DB161D-SU
• Description: IC FLASH 16MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB161D-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 16M (4096 pages x 528 bytes)
• Speed: 66MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 128 KB x 16
• Current, Input, Leakage: 1 μA
• Current, Operating: 11 mA (Read), 12 mA (Program/Erase)
• Current, Output, Leakage: 1
• Data Retention: 20 yrs.
• Density: 16M
• Package Type: EIAJ SOIC
• Temperature, Operating: -40 to +85 °C
• Time, Access: 6 ns
• Time, Address Hold: 5
• Time, Address Setup: 5
• Time, Fall: 6.8 ns
• Time, Rise: 6.8 ns
• Voltage, Input, High: 1.89 to 2.52 V
• Voltage, Input, Low: 0.81 to 1.08 V
• Voltage, Output, High: 2.5 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.7 to 3.6 V
• Memory Configuration: 4096 Pages X 528 Bytes
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.5V To 3.6V, 2.7V To 3.6V
• Rohs Compliant: Yes
• Access Time (max): 6ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.7
10
take place in a maximum time of t
the part is busy.
Table 7-2.
Chip Erase
The entire main memory can be erased at one time by using the Chip Erase command.
To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, 80H and 9AH must be clocked into
the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device,
and any data clocked in after the opcode will be ignored. After the last bit of the opcode sequence has been
clocked in, the CS pin can be deasserted to start the erase process. The erase operation is internally self-timed
and should take place in a time of t
The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors
will remain unchanged. Only those sectors that are not protected or locked down will be erased.
Note:
The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase
cycle completes.
Table 7-3.
Figure 7-1.
Note:
Command
Chip Erase
CS
PA11/
Atmel AT45DB161D
SI
A20
0
0
0
0
1
1
1
1
•
•
•
1. Refer to the errata regarding Chip Erase on
1. Refer to the errata regarding Chip Erase on
Each transition
represents eight bits
PA10/
A19
0
0
0
0
1
1
1
1
•
•
•
(1)
Sector Erase Addressing
Chip Erase Command
Chip Erase
Opcode
Byte 1
PA9/
A18
0
0
0
1
0
0
1
1
•
•
•
PA8/
A17
Opcode
0
0
1
0
0
1
0
1
Byte 2
•
•
•
SE
CE
PA7/
A16
. During this time, the status register and the RDY/BUSY pin will indicate that
X
X
X
X
X
X
. During this time, the Status Register will indicate that the device is busy.
0
0
•
•
•
Opcode
Byte 3
Byte 1
C7H
PA6/
A15
X
X
X
X
X
X
0
0
•
•
•
Opcode
page
page 53
Byte 4
PA5/
A14
X
X
X
X
X
X
0
0
•
•
•
53.
Byte 2
94H
PA4/
A13
X
X
X
X
X
X
0
0
•
•
•
PA3/
A12
X
X
X
X
X
X
0
1
Byte 3
•
•
•
80H
PA2/
A11
X
X
X
X
X
X
X
X
•
•
•
Byte 4
PA1/
A10
9AH
X
X
X
X
X
X
X
X
•
•
•
PA0/
A9
X
X
X
X
X
X
X
X
•
•
•
3500N–DFLASH–05/10
Sector
0a
0b
12
13
14
15
1
2
•
•
•