AT45DB161D-SU Atmel, AT45DB161D-SU Datasheet - Page 6

• Manufacturer Part Number: AT45DB161D-SU
• Description: IC FLASH 16MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB161D-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 16M (4096 pages x 528 bytes)
• Speed: 66MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 128 KB x 16
• Current, Input, Leakage: 1 μA
• Current, Operating: 11 mA (Read), 12 mA (Program/Erase)
• Current, Output, Leakage: 1
• Data Retention: 20 yrs.
• Density: 16M
• Package Type: EIAJ SOIC
• Temperature, Operating: -40 to +85 °C
• Time, Access: 6 ns
• Time, Address Hold: 5
• Time, Address Setup: 5
• Time, Fall: 6.8 ns
• Time, Rise: 6.8 ns
• Voltage, Input, High: 1.89 to 2.52 V
• Voltage, Input, Low: 0.81 to 1.08 V
• Voltage, Output, High: 2.5 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.7 to 3.6 V
• Memory Configuration: 4096 Pages X 528 Bytes
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.5V To 3.6V, 2.7V To 3.6V
• Rohs Compliant: Yes
• Access Time (max): 6ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2
6.3
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A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The
maximum SCK frequency allowable for the Continuous Array Read is defined by the f
Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.
Continuous Array Read (High Frequency Mode: 0BH): Up to 66MHz
This command can be used with the serial interface to read the main memory array sequentially in high speed
mode for any clock frequency up to the maximum specified by f
page size set to 528-bytes, the CS must first be asserted then an opcode 0BH must be clocked into the device
followed by three address bytes and a dummy byte. The first 12 bits (PA11 - PA0) of the 22-bit address sequence
specify which page of the main memory array to read, and the last 10 bits (BA9 - BA0) of the 22-bit address
sequence specify the starting byte address within the page. To perform a continuous read with the page size set to
512-bytes, the opcode, 0BH, must be clocked into the device followed by three address bytes (A20 - A0) and a
dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on
the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When
the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading
at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from
the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the
array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The
maximum SCK frequency allowable for the Continuous Array Read is defined by the f
Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.
Continuous Array Read (Low Frequency Mode: 03H): Up to 33MHz
This command can be used with the serial interface to read the main memory array sequentially without a dummy
byte up to maximum frequencies specified by f
528-bytes, the CS must first be asserted then an opcode, 03H, must be clocked into the device followed by three
address bytes (which comprise the 24-bit page and byte address sequence). The first 12 bits (PA11 - PA0) of the
22-bit address sequence specify which page of the main memory array to read, and the last 10 bits (BA9 - BA0) of
the 22-bit address sequence specify the starting byte address within the page. To perform a continuous read with
the page size set to 512-bytes, the opcode, 03H, must be clocked into the device followed by three address bytes
(A20 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on
the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When
the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading
at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from
the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the
array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The
Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.
Atmel AT45DB161D
CAR2
. To perform a continuous read array with the page size set to
CAR1
. To perform a continuous read array with the
CAR1
CAR1
specification. The
specification. The
3500N–DFLASH–05/10