MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet - Page 45

• Manufacturer Part Number: MT46H8M16LFCF-10 IT TR
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-10 IT TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
(auto precharge
(auto precharge
Current State
precharging
precharge)
precharge)
activating,
(with auto
(with auto
active, or
disabled)
disabled)
Write
Write
Read
Read
Row
Any
Idle
Truth Table – Current State Bank n - Command to Bank m
Notes: 1–6; notes appear below and on next page
Notes:
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted (i.e., the current state is
3. Current state definitions:
Read with auto precharge enabled: See following text – 3a
Write with auto precharge enabled: See following text – 3a
RAS#
X
H
X
H
H
H
H
H
H
H
H
H
H
the previous state was self refresh) or after
power-down).
for bank n and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that given command is allowable). Exceptions are covered in
the notes below.
3a.
states can each be broken into two parts: the access period and the precharge period. For
read with auto precharge, the precharge period is defined as if the same burst was exe-
cuted with auto precharge disabled and then followed with the earliest possible PRE-
CHARGE command that still accesses all of the data in the burst. For write with auto
L
L
L
L
L
L
L
L
L
L
CAS#
H
H
H
H
H
H
H
X
X
H
H
H
H
L
L
L
L
L
L
L
L
L
L
The read with auto precharge enabled or write with auto precharge enabled
WE#
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
Row Active: A row in the bank has been activated, and
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
Write: A WRITE burst has been initiated, with auto precharge
Read: A READ burst has been initiated, with auto precharge
Idle: The bank has been precharged, and
n-1
45
met. No data bursts/accesses and no register accesses are in
progress.
disabled, and has not yet terminated or been terminated.
disabled, and has not yet terminated or been terminated.
was HIGH and CKE
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Command/Action
t
XP has been met (if the previous state was
n
is HIGH and after
©2004 Micron Technology, Inc. All rights reserved.
t
RP has been met.
t
XSR has been met (if
t
RCD has been
Truth Tables
7, 9, 3a
Notes
7, 3a
7, 3a
7, 3a
7, 9
7, 8
7
7
7
7