MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet - Page 6

• Manufacturer Part Number: MT46H8M16LFCF-10 IT TR
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-10 IT TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
BA0, BA1
A0–A11,
CAS#
RAS#
WE#
CKE
CK#
CS#
CK
14
ADDRESS
REGISTER
Functional Block Diagram (8 Meg x 16)
STANDARD MODE
EXTENDED MODE
REGISTER
REGISTER
Notes: 1. Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
CONTROL
LOGIC
14
12
2. Complete functionality is described throughout the document and any page or dia-
3. Any specific requirement takes precedence over a general statement.
An auto-refresh mode is provided, along with a power saving power-down mode. Self
refresh mode offers temperature compensation through an on-chip temperature sensor
and partial array self refresh, which allow users to achieve additional power saving. The
temperature sensor is enabled by default and the partial array self refresh can be
programmed through the extended mode register.
term is to be interpreted as any and all DQ collectively, unless specifically stated oth-
erwise. Additionally, the x16 is divided into two bytes—the lower byte and upper byte.
For the lower byte (DQ0–DQ7) DM refers to LDM and DQS refers to LDQS; and for the
upper byte (DQ8–DQ15) DM refers to UDM and DQS refers to UDQS.
gram may have been simplified to convey a topic and may not be inclusive of all
requirements.
9
COUNTER
ADDRESS
REFRESH
2
2
ROW-
MUX
12
COUNTER/
CONTROL
COLUMN-
ADDRESS
LATCH
LOGIC
12
BANK
DECODER
ADDRESS
BANK0
LATCH
ROW-
AND
8
1
4,096
SENSE AMPLIFIERS
DM MASK LOGIC
(4,096 x 256 x 32)
I/O GATING
DECODER
COLUMN
MEMORY
ARRAY
BANK0
(x32)
8,192
256
BANK1
6
BANK2
128Mb: 8 Meg x 16 Mobile DDR SDRAM
BANK3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
32
32
32
LATCH
READ
out
CK
ck
DRIVERS
WRITE
FIFO
&
16
16
ck
in
MUX
COL0
MASK
DATA
COL0
32
4
CK
GENERATOR
2
2
16
16
REGISTERS
DQS
16
INPUT
General Description
©2004 Micron Technology, Inc. All rights reserved.
DATA
2
2
16
16
2
2
16
DQS
DRVRS
2
RCVRS
DQ0–
DQ15
LDQS
UDQS
LDM,
UDM