MT46V16M16P-75:F Micron Technology Inc, MT46V16M16P-75:F Datasheet - Page 67
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MT46V16M16P-75:F
Manufacturer Part Number
MT46V16M16P-75:F
Description
IC DDR SDRAM 256MBIT 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V16M16CY-5BK_TR.pdf
(93 pages)
Specifications of MT46V16M16P-75:F
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
256M (16Mx16)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
185mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 30:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
Command
Command
Address
Address
Address
Random READ Accesses
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
Notes:
Bank,
READ
Col n
READ
READ
Bank,
Bank,
Col n
Col n
T0
T0
T0
1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2. BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL = 8, the following burst interrupts the previous).
3. n', x', b', or g' indicate the next data-out following DO n, DO x, DO b, or DO g, respectively.
4. READs are to an active row in any bank.
5. Shown with nominal
CL = 2
Bank,
Col x
Bank,
READ
READ
READ
Bank,
Col x
Col x
T1
T1
T1
CL = 2.5
CL = 3
T2
t
AC,
Bank,
Col b
READ
READ
READ
Bank,
Bank,
Col b
Col b
T2n
T2
T2
t
DQSCK, and
DO
65
n
T2n
T3
DO
DO
n'
n
Bank,
Col g
Bank,
Col g
T3n
READ
READ
Bank,
READ
Col g
T3
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ.
DO
DO
DO
n'
n
x
T3n
T3n
T4
Transitioning Data
256Mb: x4, x8, x16 DDR SDRAM
DO
DO
DO
n'
x'
x
T4n
T4
NOP
T4
NOP
NOP
DO
DO
DO
x
x'
b
T4n
T4n
T5
DO
x'
DO
DO
b'
©2003 Micron Technology, Inc. All rights reserved.
b
T5n
T5
T5
NOP
NOP
NOP
DO
Don’t Care
DO
DO
b'
b
g
T5n
T5n
DO
Operations
b'