MT48H8M16LFB4-8 IT:J TR Micron Technology Inc, MT48H8M16LFB4-8 IT:J TR Datasheet - Page 36

• Manufacturer Part Number: MT48H8M16LFB4-8 IT:J TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-8 IT:J TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/6ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1236-2

Register Definition
Mode Register
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN
There are two mode registers in the Mobile SDRAM component, the mode register and
the extended mode register (EMR). The mode register is illustrated in Figure 14 on
page 37. The mode register defines the specific mode of operation of the Mobile SDRAM,
including burst length (BL), burst type, CAS latency (CL), operating mode, and write
burst mode. The mode register is programmed via the LOAD MODE REGISTER
command and retains the stored information until it is programmed again or the device
loses power.
Mode register bits M[2:0] specify the BL, M3 specifies the type of burst, M[6:4] specify
the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and
M10 through Mn should be set to zero to ensure compatibility with future revisions.
Mn + 1 and Mn + 2 should be set to zero to prevent the extended mode register from
being programmed.
The mode registers must be loaded when all banks are idle, and the controller must wait
t
will result in unspecified operation.
MRD before initiating the subsequent operation. Violating either of these requirements
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Register Definition