PSD813F1A-90JI STMicroelectronics, PSD813F1A-90JI Datasheet - Page 61

IC FLASH 1MBIT 90NS 52PLCC

PSD813F1A-90JI

Manufacturer Part Number
PSD813F1A-90JI
Description
IC FLASH 1MBIT 90NS 52PLCC
Manufacturer
STMicroelectronics
Datasheet

Specifications of PSD813F1A-90JI

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
1M (128K x 8)
Speed
90ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-1976-5

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0
Port C – Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 30):
Figure 30. Port C Structure
Note: 1. ISP.
MCU I/O Mode
CPLD Output – McellBC7-McellBC0 outputs
can be connected to Port B or Port C.
CPLD Input – via the Input Macrocells (IMC)
Address In – Additional high address inputs
using the Input Macrocells (IMC).
In-System Programming (ISP) – JTAG port
can be enabled for programming/erase of the
ENABLE PRODUCT TERM ( .OE )
WR
MCELLBC [ 7:0 ]
WR
CPLD - INPUT
READ MUX
DATA OUT
DIR REG.
D
D
REG.
D
B
P
Q
Q
DATA IN
SPECIAL FUNCTION
DATA OUT
Port C does not support Address Out mode, and
therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in
certain MCU interfaces.
1
PSD device. (See the section entitled
PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE, page
more information on JTAG programming.)
Open Drain – Port C pins can be configured in
Open Drain Mode
SPECIAL FUNCTION
OUTPUT
SELECT
OUTPUT
MUX
ENABLE OUT
MACROCELL
1
INPUT
CONFIGURATION
PORT C PIN
BIT
PSD813F1A
71, for
AI02888B
61/111

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