CY7C1471V33-117AXC Cypress Semiconductor Corp, CY7C1471V33-117AXC Datasheet - Page 10

• Manufacturer Part Number: CY7C1471V33-117AXC
• Description: IC SRAM 72MBIT 117MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1471V33-117AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05288 Rev. *I
Burst Write Accesses
The CY7C1471V33, CY7C1473V33, and CY7C1475V33
have an on-chip burst counter that allows the user the ability
to supply a single address and conduct up to four Write opera-
tions without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the Chip Enables
(CE
counter is incremented. The correct BW
driven in each cycle of the burst write, in order to write the
correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read
(Continue Burst)
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
3. Write is defined by BW
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQs and DQP
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQs and DQP
Parameter
Selects are asserted, see Truth Table for details.
is inactive or when the device is deselected, and DQs and DQP
1
, CE
2
Operation
, and CE
[2, 3, 4, 5, 6, 7, 8]
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
X
3
ZZREC
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
) and WE inputs are ignored and the burst
X
1
, and WE. See Truth Table for Read/Write.
, CE
after the ZZ input returns LOW.
2
, and CE
Address
External
External
Used
None
None
None
None
Next
Next
Description
3
, must remain inactive
CE
H
X
X
X
X
X
X
L
L
1
inputs must be
CE
X
X
X
H
X
H
X
L
2
X
CE
= data when OE is active.
H
X
X
X
X
X
L
L
3
ZZ ADV/LD
L
L
L
L
L
L
L
L
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table
(MODE = GND)
H
H
H
L
L
L
L
L
Address
Address
Test Conditions
DD
DD
A1: A0
A1: A0
First
First
00
01
10
11
00
01
10
11
– 0.2V
– 0.2V
WE
X
X
X
X
H
H
X
X
Address
Address
Second
Second
BW
A1: A0
A1: A0
X
X
X
X
X
X
X
X
01
00
10
01
10
00
11
11
X
OE
H
H
X
X
X
X
L
L
DD
2t
Min.
CYC
0
)
Address
Address
CEN CLK
A1: A0
A1: A0
Third
Third
L
L
L
L
L
L
L
L
10
00
01
10
00
01
CY7C1471V33
CY7C1473V33
CY7C1475V33
11
11
L->H
L->H
L->H
L->H
L->H Data Out (Q)
L->H Data Out (Q)
L->H
L->H
2t
2t
Max.
150
X
CYC
CYC
= Tri-state when OE
Page 10 of 29
Address
Address
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Fourth
A1: A0
Fourth
A1: A0
DQ
11
10
01
00
11
00
01
10
Unit
mA
ns
ns
ns
ns