CY7C1471V33-117AXC Cypress Semiconductor Corp, CY7C1471V33-117AXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1471V33-117AXC
• Description: IC SRAM 72MBIT 117MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1471V33-117AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05288 Rev. *I
Pin Definitions
Functional Overview
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
synchronous flow-through burst SRAMs designed specifically
to eliminate wait states during Write-Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (t
device).
Accesses can be initiated by asserting all three Chip Enables
(CE
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BW
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Burst Read Accesses
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 have
an on-chip burst counter that allows the user the ability to
1
, CE
Name
TMS
TCK
NC
3
2
are ALL asserted active, (3) the Write Enable input
, CE
3
) active at the rising edge of the clock. If Clock
JTAG serial input
(continued)
Synchronous
-Clock
JTAG
I/O
-
CDV
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V
No Connects. Not internally connected to the die. 144M, 288M, 576M and 1G are address
expansion pins and are not internally connected to the die.
1
) is 6.5 ns (133-MHz
, CE
X
can be used to
2
, CE
3
) and an
1
, CE
SS
. This pin is not available on TQFP packages.
2
,
supply a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and will wrap around when incre-
mented sufficiently. A HIGH input on ADV/LD will increment
the internal burst counter regardless of the state of chip enable
inputs or WE. WE is latched at the beginning of a burst cycle.
Therefore, the type of access (Read or Write) is maintained
throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The Write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQP
On the next clock rise the data presented to DQs and DQP
(or a subset for Byte Write operations, see Truth Table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW
CY7C1475V33 provides Byte Write capability that is described
in the Truth Table. Asserting the Write Enable input (WE) with
the selected Byte Write Select input will selectively write to
only the desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the Write
operations. Byte Write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple byte write operations.
Because
CY7C1475V33 are common I/O devices, data should not be
driven into the device while the outputs are active. The Output
Enable (OE) can be deasserted HIGH before presenting data
to the DQs and DQP
drivers. As a safety precaution, DQs and DQP
cally tri-stated during the data portion of a write cycle,
regardless of the state of OE.
X
signals. The CY7C1471V33, CY7C1473V33 and
3
are ALL asserted active, and (3) the Write signal WE
Description
the
X
.
CY7C1471V33,
X
inputs. Doing so will tri-state the output
CY7C1471V33
CY7C1473V33
CY7C1475V33
CY7C1473V33
DD
. This pin is not
X
Page 9 of 29
are automati-
1
, CE
and
2
X
,