CY7C1471V33-117AXC Cypress Semiconductor Corp, CY7C1471V33-117AXC Datasheet - Page 8

• Manufacturer Part Number: CY7C1471V33-117AXC
• Description: IC SRAM 72MBIT 117MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1471V33-117AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05288 Rev. *I
Pin Definitions
BW
BW
BW
A
D
A
ADV/LD
, BW
, BW
MODE
Name
0
DQP
V
CEN
TDO
CLK
CE
CE
CE
DQ
V
, A
V
G
WE
TDI
OE
ZZ
DDQ
, BW
DD
SS
1
B
E
1
2
3
s
, A
X
, BW
, BW
H
C
F
,
,
I/O Power Supply Power supply for the I/O circuitry.
JTAG serial input
Input Strap Pin Mode Input. Selects the burst order of the device.
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
JTAG serial
Ground
output
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
I/O-
I/O-
I/O
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK. A
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access. After being deselected,
ADV/LD should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by
the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when required.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. During normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQ
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ
During write sequences, DQP
When tied to Gnd selects linear burst sequence. When tied to V
interleaved burst sequence.
Power supply inputs to the core of the device.
Ground for the device.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be left floating or connected to V
resistor. This pin is not available on TQFP packages.
2
1
1
, and CE
and CE
and CE
[1:0]
3
2
are fed to the two-bit burst counter.
3
to select/deselect the device.
to select/deselect the device.
to select/deselect the device.
X
is controlled by BW
Description
s
and DQP
X
X
are placed in a tri-state condition.The
correspondingly.
DD
DD
CY7C1471V33
CY7C1473V33
CY7C1475V33
or left floating selects
through a pull up
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s
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