TE28F800C3BD70 Intel, TE28F800C3BD70 Datasheet
TE28F800C3BD70
Specifications of TE28F800C3BD70
Related parts for TE28F800C3BD70
TE28F800C3BD70 Summary of contents
Page 1
... Additional information on this product family can be obtained by accessing the Intel Flash website: http://www.intel.com/design/flash. Notice: This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. 128-bit Protection Register — ...
Page 2
... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...
Page 3
... Document Purpose ...............................................................................................................7 1.2 Nomenclature .......................................................................................................................7 1.3 Conventions..........................................................................................................................7 2.0 Device Description ........................................................................................................................8 2.1 Product Overview .................................................................................................................8 2.2 Ballout Diagram ....................................................................................................................8 2.3 Signal Descriptions .............................................................................................................13 2.4 Block Diagram ....................................................................................................................14 2.5 Memory Map .......................................................................................................................15 3.0 Device Operations .......................................................................................................................17 3.1 Bus Operations ...................................................................................................................17 3.1.1 Read ......................................................................................................................17 3.1.2 Write ......................................................................................................................17 3.1.3 Output Disable .......................................................................................................17 3.1.4 Standby..................................................................................................................18 3.1.5 Reset .....................................................................................................................18 4.0 Modes of Operation ...
Page 4
Contents 5.6.1 Program Protection................................................................................................ 31 6.0 Power Consumption.................................................................................................................... 32 6.1 Active Power (Program/Erase/Read).................................................................................. 32 6.2 Automatic Power Savings (APS) ........................................................................................ 32 6.3 Standby Power ................................................................................................................... 32 6.4 Deep Power-Down Mode.................................................................................................... 32 6.5 Power and Reset Considerations ....................................................................................... 33 6.5.1 ...
Page 5
... Maximum Specification change (Section 4.3) IL -003 I test conditions clarification (Section 4.3) CCS Added Command Sequence Error Note (Table 7) Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash Memory Family. Added t /t and t BHWH BHEH -004 Programming the Protection Register clarification (Section 3.4.2) ...
Page 6
Contents Date of Revision 4/05/02 3/06/03 10/03 6 Version Updated 64Mb product offerings. Updated 16Mb product offerings. -014 Revised and corrected DC Characteristics Table. Added mechanicals for Easy BGA. Minor text edits throughout document. -016 Complete technical update. -017 ...
Page 7
... Introduction 1.1 Document Purpose This datasheet contains the specifications for the Intel (C3) device family. These flash memories add features such as instant block locking and protection registers that can be used to enhance the security of systems. 1.2 Nomenclature ...
Page 8
... Intel Advanced+ Boot Block Flash Memory (C3) 2.0 Device Description This section provides an overview of the Intel features, packaging, signal naming, and device architecture. 2.1 Product Overview The C3 device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’ ...
Page 9
... Figure 1. 48-Lead TSOP Package NOTES: 1. For lower densities, upper address should be treated as NC. For example, a 16-Mbit device will have NC on Pins 9 and 10. Datasheet Intel Advanced+ Boot Block 20 WE £ Advanced+ Boot Block Flash Memory (C3) ...
Page 10
... TSOP products will convert to a white ink triangle as a Pin 1 indicator. Products without the white triangle will continue to use a dimple as a Pin 1 indicator. There are no other changes in package size, materials, functionality, customer handling, or manufacturability. Product will continue to meet Intel stringent quality requirements. Products affected are Intel Ordering Codes shown in Table Table 1 ...
Page 11
... D14 E V D15 CCQ F GND D7 NOTES: 1. Shaded connections indicate the upgrade address connections. Routing is not recommended in this area. 2. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit. 3. Unused address balls are not populated. Datasheet Intel 1,2 VPP WE# RP# 64M 32M A9 A21 ...
Page 12
... Intel Advanced+ Boot Block Flash Memory (C3) Figure 4. 64-Ball Easy BGA Package ( RP WP SSQ 2 H ( CCQ CC Top View - Ball Side NOTES: 1. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit. 2. Unused address balls are not populated. ...
Page 13
... CONNECT: Pin must be left floating. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Name and Function for details on block locking. VPPLK to protect all contents against Program and Erase commands. 5% for faster program and erase in a production environment. Applying range ...
Page 14
... Intel Advanced+ Boot Block Flash Memory (C3) 2.4 Block Diagram A[MAX:MIN CCQ Output Buffer Identifier Register Status Register Power Reduction Comparator Control Y-Decoder Y-Gating/Sensing Input Buffer Address Latch X-Decoder Address Counter - Input Buffer I/O Logic ...
Page 15
... Datasheet Intel Table 3, “Top Boot Memory Map” on page 15 for details. 16-Mbit Size Memory Size Blk (KW) Addressing (KW) (HEX FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF ...
Page 16
... Intel Advanced+ Boot Block Flash Memory (C3) Table 4. Bottom Boot Memory Map 8-Mbit Size Memory Size Blk (KW) Addressing (KW) (HEX 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 32 ... ... ... ... 32 10 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 4 6 06000-06FFF 4 5 05000-05FFF 4 4 04000-04FFF 4 3 03000-03FFF ...
Page 17
... Address and data are latched on the rising edge of the WE# or CE# pulse, whichever occurs first. See 3.1.3 Output Disable With OE logic - high level (V high - impedance state. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Table 5 on page 17 summarizes these bus operations. Bus Operations Mode RP# Read ...
Page 18
... Block-Erase operations CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
Page 19
... Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in retrieve the specified information. To return to read-array mode, issue the Read Array command (0xFF). Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) and Table 8, “Command Codes and summarize the commands used to reach these modes. ...
Page 20
... Intel Advanced+ Boot Block Flash Memory (C3) Table 6. Device Identification Codes Item Manufacturer ID Device ID Block Lock Status Block Lock-Down Status Protection Register Lock Status Protection Register NOTES: 1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block number bottom boot device, set the address to 0x0F8000 plus the offset (0x02), i ...
Page 21
... VPP pin. This eliminates the need for an external switching transistor to control V flash power supplies can be configured for various usage models. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) 26). was not within acceptable limits, and the WSM did not execute the program PP ...
Page 22
... Intel Advanced+ Boot Block Flash Memory (C3) The found in manufacturing processes; however not intended for extended use may be applied to VPP during Program and Erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected for a total of 80 hours maximum ...
Page 23
... Resume, Lock Block, Unlock Block, and Lock-Down Block. During erase-suspend mode, the chip can be placed in a pseudo - standby mode by taking CE consumption. Erase Resume continues the erase sequence when CE Erase operation, the status register should be read and cleared before the next instruction is issued. Datasheet Intel /t . WHRH2 EHRH2 £ ...
Page 24
... NOTES: 1. Following the Read Identifier or CFI Query commands, read operations output device identification data or CFI query information, respectively. See 2. Either 0x40 or 0x10 command is valid, but the Intel standard is 0x40. 3. When writing commands, the upper data bus [DQ8-DQ15] should be either V draw. Bus operations are defined in ...
Page 25
... C0 Program Set-Up Datasheet £ Intel Command Description This command places the device in read-array mode, which outputs array data on the data pins. This is a two - cycle command. The first cycle prepares the CUI for a program operation. The second cycle latches addresses and data information and initiates the WSM to execute the Program algorithm ...
Page 26
... NOTE: A Command-Sequence Error is indicated when SR[4], SR[5], and SR[7] are set. 26 Command Description Operates the same as Program Set - up command. (See 0x40/Program Set-Up) Unassigned commands should not be used. Intel reserves the right to redefine these codes for future functions. for mode transition information. ES ...
Page 27
... Block Lock status register, and c = bit D0 of the Block Lock status register. Locking State Diagram” on page 27 Figure 5. Block Locking State Diagram Power-Up/Reset Notes: Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) displays all of the possible locking states. Locked [X01] Unlocked [X00] ...
Page 28
... Intel Advanced+ Boot Block Flash Memory (C3) 5.1.1 Locking Operation The locking status of each block can be set to Locked, Unlocked, or Lock-Down, each of which will be described in the following sections. See page 27 and Figure 17, “Locking Operations Flowchart” on page The following concisely summarizes the locking functionality ...
Page 29
... Boot Block Flash Memory Architecture, contains additional application information. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designs to program, as preferred. Once the customer segment is programmed, it can be locked to prevent further programming ...
Page 30
... The user-programmable segment of the protection register is lockable by programming bit 1 of the PR-LOCK location to 0. See location is programmed the Intel factory to protect the unique device number. This bit is set using the Protection Program command to program 0xFFFD to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register ...
Page 31
... Low Voltage and 12 V Fast Programming NOTE resistor can be used if the V Designing with the Advanced+ Boot Block Flash Memory Architecture for details. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) programming voltage can be held low for absolute PP System Supply System Supply ...
Page 32
... Power Consumption Intel Flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If CE# is deasserted, the flash enters its standby mode, where current consumption is even lower ...
Page 33
... If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. ...
Page 34
... These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended, and extended exposure beyond the “Operating Conditions” may affect device reliability. . NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design Extended Operating Temperature ...
Page 35
... DC Current Characteristics Table 11. DC Current Characteristics (Sheet Sym I Input Load Current LI Output Leakage I LO Current Datasheet Intel Parameter Operating Temperature V Supply Voltage CC I/O Supply Voltage Supply Voltage Block Erase Cycling must share the same supply when they are in the V CCQ = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on ...
Page 36
... Intel Advanced+ Boot Block Flash Memory (C3) Table 11. DC Current Characteristics (Sheet Sym V Standby Current CC for 0.13 and 0.18 Micron Product I CCS V Standby Current CC for 0.25 Micron Product V Power-Down CC Current for 0.13 and 0.18 Micron Product ...
Page 37
... All currents are in RMS unless otherwise noted. Typical values at nominal V 2. The test conditions V V voltage listed at the top of each column. V CCQ 3. Automatic Power Savings (APS) reduces I inputs). 4. Sampled, not 100% tested CCES is sum of I and I CCR Datasheet Intel V 2.7 V–3 Parameter V 2.7 V–3.6 V CCQ Note Typ 2 Read Current 1,4 50 0.05 ...
Page 38
... Intel Advanced+ Boot Block Flash Memory (C3) 7.4 DC Voltage Characteristics Table 12. DC Voltage Characteristics V CC Sym Parameter V CCQ Note Input Low V IL Voltage Input High V IH Voltage Output Low V OL Voltage Output High V OH Voltage ...
Page 39
... OH Change, Whichever Occurs First NOTES: 1. OE# may be delayed Sampled, but not 100% tested. 3. See Figure 8, “Read Operation Waveform” on page 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 slew rate. Datasheet Intel Density Product 3.0 V – 3 Note Min Max 3,4 80 3,4 ...
Page 40
... Intel Advanced+ Boot Block Flash Memory (C3) Table 14. Read Operations—16 Mbit Density Density Product Para- # Sym mete r 2.7 V–3 Min R1 t Read Cycle Time AVAV t Address to AVQ R2 Output Delay V t CE# to Output ELQ R3 Delay ...
Page 41
... Occurs First NOTES: 1. OE# may be delayed Sampled, but not 100% tested. 3. See Figure 8, “Read Operation Waveform” on page 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 input slew rate. Datasheet Intel 2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.3 V Min Max Min Max ...
Page 42
... Intel Advanced+ Boot Block Flash Memory (C3) Table 16. Read Operations — 64 Mbit Density # Sym R1 t AVAV R2 t AVQV R3 t ELQV R4 t GLQV R5 t PHQV R6 t ELQX R7 t GLQX R8 t EHQZ R9 t GHQZ R10 t OH NOTES: 1 ...
Page 43
... Table 7, “Command Bus Operations” on page 24 3. Sampled, but not 100% tested. 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 slew rate. 5. See Figure 9, “Write Operations Waveform” on page Datasheet Intel Density Product Parameter 3.0 V – 3 2.7 V – 3.6 V Setup to WE# (CE#) Going High ...
Page 44
... Intel Advanced+ Boot Block Flash Memory (C3) Table 18. Write Operations—16 Mbit Density # Sym Parameter t / RP# High Recovery to WE# (CE#) Going PHWL W1 t Low PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t WLEL t / WLWH W3 WE# (CE#) Pulse Width ...
Page 45
... Sampled, but not 100% tested. 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 slew rate. 5. See Figure 9, “Write Operations Waveform” on page 6. V Max = 3.3 V for 32-Mbit 0.25 Micron product. CC Datasheet Intel Density Product 3.0 V – 3 2.7 V – 3.6 V Note Min ...
Page 46
... Intel Advanced+ Boot Block Flash Memory (C3) Table 20. Write Operations—64Mbit Density # Sym t / PHWL W1 t PHEL t / ELWL W2 t WLEL t / WLWH W3 t ELEH t / DVWH W4 t DVEH t / AVWH W5 t AVEH t / WHEH W6 t EHWH t / WHDX W7 t EHDX t / WHAX ...
Page 47
... EHQV3 WHRH1 EHRH1 WHRH2 EHRH2 NOTES: 1. Typical values measured Excludes external system-level overhead. 3. Sampled, but not 100% tested. Datasheet £ Intel W10 Parameter Note 4-KW Parameter Block Word Program Time 32-KW Main Block Word Program Time Word Program Time for 0. and 0 ...
Page 48
... Intel Advanced+ Boot Block Flash Memory (C3) 8.4 Reset Specifications Table 22. Reset Specifications Symbol RP# Low to Reset during Read t (If RP# is tied to V PLPH applicable) t RP# Low to Reset during Block Erase PLRH1 t RP# Low to Reset during Program ...
Page 49
... Min Standard Test CCQ NOTE: C includes jig capacitance. L 8.6 Device Capacitance ° MHz A Symbol OUT § Sampled, not 100% tested. Datasheet £ Intel Input V /2 CCQ = V CC Device Under Test C § Parameter Typ Input Capacitance Output Capacitance Advanced+ Boot Block Flash Memory (C3 CCQ /2. Input rise and fall times (10% to 90%) < ...
Page 50
... Intel Advanced+ Boot Block Flash Memory (C3) Appendix A Write State Machine States This table shows the command state transitions based on incoming commands. Data Current State SR.7 When Read Read Array “1” Array Read Status “ ...
Page 51
... Erase Suspend Config Read Config. Eras Sus. Read Erase Suspend Query Read Config. Ers.(Done) Read Config. Datasheet £ Intel Command Input (and Next State) Lock Setup Read Query Prot. Prog. (60H) (98H) Setup (C0H) Read Query Lock Setup Prot. Prog. Setup ...
Page 52
... Intel Advanced+ Boot Block Flash Memory (C3) Appendix B Flow Charts Figure 13. Word Program Flowchart Start Write 0x40, Word Address Write Data, Word Address Read Status Register SR[ Full Status Check (if desired) Program Complete Read Status Register ...
Page 53
... SR[ Write 0xFF Read Array Data Done Reading Yes Write 0xD0 Any Address Program Resumed Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) PROGRAM SUSPEND / RESUME PROCEDURE Operation Command (Program Suspend) (Read Status) 0 Program 0 Completed (Read Array) (Read Write 0xFF Array) Read Array ...
Page 54
... Intel Advanced+ Boot Block Flash Memory (C3) Figure 15. Erase Suspend / Resume Flowchart (Read Array) (Erase Resume) 54 ERASE SUSPEND / RESUME PROCEDURE Start Write 0xB0, (Erase Suspend) Any Address Write 0x70, (Read Status) Any Address Read Status ...
Page 55
... Read Status Register SR[ SR[4, SR[ SR[ Block Erase Successful Datasheet £ Intel BLOCK ERASE PROCEDURE Operation Command (Block Erase) (Erase Confirm) Suspend Erase Loop No Suspend 0 Yes Erase Repeat for subsequent block erasures. Full Status register check can be done after each block erase or after a sequence of block erasures ...
Page 56
... Intel Advanced+ Boot Block Flash Memory (C3) Figure 17. Locking Operations Flowchart Start Write 0x60, Block Address Write either 0x01/0xD0/0x2F, Block Address Write 0x90 Read Block Lock Status Locking Change? Write 0xFF Any Address Lock Change ...
Page 57
... Register SR[7] = Full Status Check (if desired) Program Complete Read Status Register Data SR[3], SR[4] = SR[3], SR[4] = SR[3], SR[4] = Program Successful Datasheet Intel PROTECTION REGISTER PROGRAMMING PROCEDURE (Program Setup) (Confirm Data FULL STATUS CHECK PROCEDURE 1 V Range Error Program Error 0 Register Locked; ...
Page 58
... Intel Advanced+ Boot Block Flash Memory (C3) Appendix C Common Flash Interface This appendix defines the data structure or “database” returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications ...
Page 59
... BA = Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is 32K-word). 3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table. C.3 Block Status Register The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations ...
Page 60
... Intel Advanced+ Boot Block Flash Memory (C3) Table 27. Block Status Register Offset Length 1 0x(BA+2) NOTES Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is 32K-word). C.4 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification ...
Page 61
... Erase Block Region 2 Information bits 0– y+1 = number of identical-size erase blocks 0x2D 14 bits 16– region erase block(s) size are z x 256 bytes Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Description n µs n µs n ...
Page 62
... C.6 Intel-Specific Extended Query Table Certain flash features and commands are optional. The Intel - Specific Extended Query table specifies this and other similar types of information. Table 32. Primary-Vendor Specific Extended Query (Sheet Offset Length P = 0x15 0x(P+0) ...
Page 63
... Reserved for future use NOTES: 1. The variable pointer which is defined at CFI offset 0x15. Datasheet Intel Description (Optional Flash Features and Commands) Supported functions after suspend: Read Array, Status, Query Other supported operations are: bits 1–7 reserved; undefined bits are “0” ...
Page 64
... Intel Advanced+ Boot Block Flash Memory (C3) Appendix D Mechanical Specifications Figure 19. BGA* and VF BGA Package Drawing & Dimensions Ball A1 Corner Top View - Bump Side down Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length 8M ( ...
Page 65
... One dimple on package denotes Pin two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark. 4. Pin 1 will always supersede above pin one notes. Datasheet Intel Z See Notes and ...
Page 66
... Intel Advanced+ Boot Block Flash Memory (C3) Figure 21. Easy BGA Package Drawing & Dimension Ball A1 Corner Dimensions Table Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch ...
Page 67
... Contact your Intel Representative 297874 NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at ‘http://www.intel.com/design/flash’ for technical documentation and tools. ...
Page 68
... Figure 22. Component Ordering Information Package TE = 48-Lead TSOP GT = 48-Ball µBGA* CSP BGA CSP RC = Easy BGA Product line designator ® for all Intel Flash products Device Density 640 = x16 (64 Mbit) 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) VALID COMBINATIONS (All Extended Temperature) Extended ...
Page 69
This datasheet has been downloaded from: 100% Free Datasheet Search Site 100% Free IC Replacement Search Site Convenient Electronic Dictionary www.EEworld.com.cn Free Download Daily Updated Database Fast Search System www.EEworld.com.cn All Datasheets Cannot Be Modified Without Permission Copyright © ...