L6566B STMicroelectronics, L6566B Datasheet - Page 25

IC CTRLR OVP OTP UVLO HV 16SOIC

L6566B

Manufacturer Part Number
L6566B
Description
IC CTRLR OVP OTP UVLO HV 16SOIC
Manufacturer
STMicroelectronics
Datasheet

Specifications of L6566B

Output Isolation
Isolated
Frequency Range
10 ~ 300kHz
Voltage - Input
8 ~ 23 V
Power (watts)
750mW
Operating Temperature
-40°C ~ 150°C
Package / Case
16-SOIC (0.154", 3.90mm Width)
Output Current
800 mA
Output Power
750 mW
Input Voltage
8 V to 23 V
Operating Temperature Range
- 40 C to + 150 C
Mounting Style
SMD/SMT
Duty Cycle (max)
75 %
Selectable Multi-mode Operation
fixed frequency or quasi-resonant
For Use With
497-6452 - BOARD EVAL FOR L6566B497-6451 - BOARD EVAL FOR L6566B497-6450 - BOARD EVAL FOR L6566B497-6449 - BOARD EVAL FOR L6566A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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L6566B
5.4
Figure 13.
COMP
(*) Vcc
9
V
V
COMPL
COMPO
OFF2
< Vcc
-
+
Figure 12. Addition of an offset to the current sense lowers the burst-mode
Adaptive UVLO
A major problem when optimizing a converter for minimum no-load consumption is that the
voltage generated by the auxiliary winding under these conditions falls considerably as
compared even to a few mA load. This very often causes the supply voltage Vcc of the
control IC to drop and go below the UVLO threshold so that the operation becomes
intermittent, which is undesired. Furthermore, this must be traded off against the need of
generating a voltage not exceeding the maximum allowed by the control IC at full load.
To help the designer overcome this problem, the device, besides reducing its own
consumption during burst-mode operation, also features a proprietary adaptive UVLO
function. It consists of shifting the UVLO threshold downwards at light load, namely when
the voltage at pin COMP falls below a threshold V
headroom. To prevent any malfunction during transients from minimum to maximum load
the normal (higher) UVLO threshold is re-established when the voltage at pin COMP
exceeds V
normal UVLO threshold ensures that at full load the MOSFET will be driven with a proper
gate-to-source voltage.
Adaptive UVLO block
OFF1
is selected when Q is high
COMPL
operation threshold
R
S
and Vcc has exceeded the normal UVLO threshold (see
Vcc
Q
OFF1
+
-
Vref
Vcc
L6566B
SW
(*)
OFF2
Vcc
10
5
+
-
3
UVLO
L6566B
7
4
Vcs
o
= Vref
COMPO
VCOMP
Rc
(pin 9)
(pin 5)
Vcc
Vcc
V
V
Vcc
R + Rc
COMPL
COMPO
OFF1
OFF2
Q
R
R
internally fixed, so as to have more
Application information
Rs
Figure 13
). The
25/51
t
t
t

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