PCF8576CT/1,118 NXP Semiconductors, PCF8576CT/1,118 Datasheet - Page 25

• Manufacturer Part Number: PCF8576CT/1,118
• Description: IC LCD DVR UNVRSL LOW-MUX 56VSOP
• Manufacturer: NXP Semiconductors

Specifications of PCF8576CT/1,118

• Package / Case: 56-VSOP
• Display Type: LCD
• Configuration: 40 Segment
• Interface: I²C
• Current - Supply: 120µA
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 20
• Number Of Segments: 160
• Maximum Clock Frequency: 315 KHz
• Operating Supply Voltage: 2 V to 6 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 150 C
• Maximum Supply Current: 120 uA
• Minimum Operating Temperature: - 65 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1080-2; 935278818118; PCF8576CTD-T

NXP Semiconductors
PCF8576C
Product data sheet
7.16.3 System configuration
7.16.4 Acknowledge
A device generating a message is a transmitter and a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is illustrated in
Figure
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
Acknowledgement on the I
Fig 17. System configuration
•
•
•
•
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
SCL
SDA
17.
TRANSMITTER/
RECEIVER
MASTER
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 22 July 2010
RECEIVER
2
C-bus is illustrated in
SLAVE
TRANSMITTER/
RECEIVER
Universal LCD driver for low multiplex rates
SLAVE
Figure
TRANSMITTER
18.
MASTER
PCF8576C
TRANSMITTER/
© NXP B.V. 2010. All rights reserved.
RECEIVER
MASTER
mga807
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