ADE7753ARSZ Analog Devices Inc, ADE7753ARSZ Datasheet - Page 36

• Manufacturer Part Number: ADE7753ARSZ
• Description: IC ENERGY METERING 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7753ARSZ

• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• Ic Function: Single-Phase Multifunction Metering IC
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADE7753ZEB - BOARD EVALUATION AD7753
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADE7753
Note that the apparent energy register is unsigned—see Figure 76.
By using the interrupt enable register, the ADE7753 can be con-
figured to issue an interrupt ( IRQ ) when the apparent energy
register is half full or when an overflow occurs. The half full
interrupt for the unsigned apparent energy register is based on
24 bits as opposed to 23 bits for the signed active energy register.
Integration Times under Steady Load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.1 µs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
VAGAIN register set to 0x000, the average word value from
apparent power stage is 0xAD055—see the Apparent Power
Calculation section. The maximum value that can be stored in
the apparent energy register before it overflows is 2
0xFF,FFFF. The average word value is added to the internal
register, which can store 2
overflows. Therefore, the integration time under these conditions
with VADIV = 0 is calculated as follows:
When VADIV is set to a value different from 0, the integration
time varies, as shown in Equation 33.
Time =
Time = Time
0
xFFFF,
CHANNEL 2
WDIV = 0
0
xD
FROM
FFFF,
ADC
055
× VADIV
48
or 0xFFFF,FFFF,FFFF before it
FFFF
LPF1
× 1.2 µs = 888 s = 12.52 min (32)
ZERO-CROSSING
APPARENT
DETECTION
POWER
Figure 77. ADE7753 Apparent Energy Calibration
24
or
VADIV[7:0]
%
LINECYC [15:0]
CALIBRATION
Rev. A | Page 36 of 60
CONTROL
(33)
+
+
LINE APPARENT ENERGY ACCUMULATION
The ADE7753 is designed with a special apparent energy
accumulation mode, which simplifies the calibration process.
By using the on-chip zero-crossing detection, the ADE7753
accumulates the apparent power signal in the LVAENERGY
register for an integral number of half cycles, as shown in
Figure 77. The line apparent energy accumulation mode is
always active.
The number of half line cycles is specified in the LINCYC
register, which is an unsigned 16-bit register. The ADE7753 can
accumulate apparent power for up to 65535 combined half
cycles. Because the apparent power is integrated on the same
integral number of line cycles as the line active energy register,
these two values can be compared easily. The active energy and
the apparent energy are calculated more accurately because of
this precise timing control and provide all the information
needed for reactive power and power factor calculation. At the
end of an energy calibration cycle, the CYCEND flag in the
interrupt status register is set. If the CYCEND mask bit in the
interrupt mask register is enabled, the IRQ output also goes
active low. Thus the IRQ line can also be used to signal the end
of a calibration.
The line apparent energy accumulation uses the same signal
path as the apparent energy accumulation. The LSB size of these
two registers is equivalent.
48
23
LVAENERGY [23:0]
0
LVAENERGY REGISTER IS
UPDATED EVERY LINECYC
ZERO CROSSINGS WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
0
02875-0-076