ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 71

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Address
0x4399
0x439A
0x439B
0x439C
0x439D
0x439E
0x439F
0x43A0
0x43A1
0x43A2
0x43A3
0x43A4
0x43A5
0x43A6
0x43A7
0x43A8
0x43A9
Register
Name
BVARGAIN
BVAROS
CVARGAIN
CVAROS
AFWGAIN
AFWATTOS
BFWGAIN
BFWATTOS
CFWGAIN
CFWATTOS
AFVARGAIN
AFVAROS
BFVARGAIN
BFVAROS
CFVARGAIN,
CFVAROS
VATHR1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
Bit Length
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
Rev. 0 | Page 71 of 92
Bit Length During
Communication
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZP
2
Type
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
U
3
Default
Value
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
Description
Phase B total
reactive power gain
adjust.
Phase B total
reactive power offset
adjust.
Phase C total
reactive power gain
adjust.
Phase C total
reactive power offset
adjust.
Phase A fundamental
active power gain
adjust.
Phase A fundamental
active power offset
adjust.
Phase B fundamental
active power gain
adjust.
Phase B fundamental
active power offset
adjust.
Phase C fundamental
active power gain
adjust.
Phase C fundamental
active power offset
adjust.
Phase A fundamental
reactive power gain
adjust.
Phase A fundamental
reactive power offset
adjust.
Phase B fundamental
reactive power gain
adjust.
Phase B fundamental
reactive power offset
adjust.
Phase C fundamental
reactive power gain
adjust.
Phase C fundamental
reactive power offset
adjust.
Most significant
24 bits of
VATHR[47:0]
threshold used in
phase apparent
power datapath.
ADE7878