ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 79

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
Location
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
31:25
Table 33. MASK0 Register (Address 0xE50A)
Bit
Location
0
1
2
3
4
5
Bit Name
ZXTOVC
ZXTOIA
ZXTOIB
ZXTOIC
ZXVA
ZXVB
ZXVC
ZXIA
ZXIB
ZXIC
RSTDONE
SAG
OI
OV
SEQERR
MISMTCH
(Reserved)
(Reserved)
PKI
PKV
Reserved
Bit Name
AEHF
FAEHF
REHF
FREHF
VAEHF
LENERGY
Default Value
0
0
0
0
0
0
Default Value
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
000 0000
Description
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total active energy
registers (AWATTHR, BWATTHR, CWATTHR) changes.
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental active
energy registers (AFWATTHR, BFWATTHR, or CFWATTHR) changes.
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total reactive
energy registers (AVARHR, BVARHR, CVARHR) changes.
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental
reactive energy registers (AFVARHR, BFVARHR, or CFVARHR) changes.
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the apparent energy
registers (AVAHR, BVAHR, CVAHR) changes.
When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end of
an integration over an integer number of half-line cycles set in the LINECYC[15:0] register.
When this bit is set to 1, it indicates that a zero crossing on Phase C voltage is missing.
When this bit is set to 1, it indicates that a zero crossing on Phase A current is missing.
When this bit is set to 1, it indicates that a zero crossing on Phase B current is missing.
When this bit is set to 1, it indicates that a zero crossing on Phase C current is missing.
When this bit is set to 1, it indicates that a zero crossing has been detected on Phase A voltage.
When this bit is set to 1, it indicates that a zero crossing has been detected on Phase B voltage.
When this bit is set to 1, it indicates that a zero crossing has been detected on Phase C voltage.
When this bit is set to 1, it indicates that a zero crossing has been detected on Phase A current.
When this bit is set to 1, it indicates that a zero crossing has been detected on Phase B current.
When this bit is set to 1, it indicates that a zero crossing has been detected on Phase C current.
In case of a software reset command, Bit 7 (SWRST) is set to 1 in the CONFIG[15:0] register, or
a transition from PSM1, PSM2, or PSM3 to PSM0, or a hardware reset, this bit is set to 1 at the
end of the transition process and after all registers changed value to the default. The IRQ1
pin goes low to signal this moment because this interrupt cannot be disabled.
When this bit is set to 1, it indicates a SAG event has occurred on one of the phases indicated
by Bits[14:12] (VSPHASE) in the PHSTATUS[15:0] register (see Table 35).
When this bit is set to 1, it indicates an overcurrent event has occurred on one of the phases
indicated by Bits[5:3] (OIPHASE) in the PHSTATUS[15:0] register (see Table 35).
When this bit is set to 1, it indicates an overvoltage event has occurred on one of the phases
indicated by Bits[11:9] (OVPHASE) in the PHSTATUS[15:0] register (see Table 35).
When this bit is set to 1, it indicates a negative-to-positive zero crossing on the Phase A
voltage was not followed by a negative-to-positive zero crossing on the Phase B voltage but
by a negative-to-positive zero crossing on the Phase C voltage.
When this bit is set to 1, it indicates
indicated in the ISUMLVL[23:0] register.
Reserved. This bit is always set to 1.
Reserved. This bit is always set to 0.
When this bit is set to 1, it indicates that the period used to detect the peak value in the
current channel has ended. The IPEAK[31:0] register contains the peak value and the phase
where the peak has been detected (see Table 29).
When this bit is set to 1, it indicates that the period used to detect the peak value in the
voltage channel has ended. The VPEAK[31:0] register contains the peak value and the phase
where the peak has been detected (see Table 30).
Reserved. These bits are always 0.
Description
Rev. 0| Page 79 of 92
ISUM
−
INWV
>
ISUMLVL
, where ISUMLVL is
ADE7878