ADE7763ARS Analog Devices Inc, ADE7763ARS Datasheet - Page 48

• Manufacturer Part Number: ADE7763ARS
• Description: IC ENERGY METER 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7763ARS

• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7763ZEB - BOARD EVALUATION FOR ADE7763
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADE7763
Address
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
Name
WGAIN
WDIV
CFNUM
CFDEN
IRMS
VRMS
IRMSOS
VRMSOS
VAGAIN
VADIV
LINECYC
ZXTOUT
SAGCYC
SAGLVL
IPKLVL
VPKLVL
IPEAK
RSTIPEAK
VPEAK
RSTVPEAK
TEMP
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
No. Bits
12
8
12
12
24
24
12
12
12
8
16
12
8
8
8
8
24
24
24
24
8
Default
0x0
0x0
0x3F
0x3F
0x0
0x0
0x0
0x0
0x0
0x0
0
0xFFF
0xFF
0x0
0xFF
0xFF
0x0
0x0
0x0
0x0
0x0
xFFFF
Type
S
U
U
U
U
U
S
S
S
U
U
U
U
U
U
U
U
U
U
U
S
Rev. A | Page 48 of 56
1
Description
Power Gain Adjust. This is a 12-bit register. Calibrate the active power
calculation by writing to this register. The calibration range is ±50% of
the nominal fu
0.0244%/LSB —see the Calibrating an Energy Meter section.
Active Energy Divider Register. The internal active energy register is
divided by the value of this register before being stored in the AENER
register.
CF Frequency Divider Numerator Register. Ad
on the CF pin by writing to this 12-bit read/write register—see the
Energy-to-Frequency Conversion section.
CF Frequ
frequency on the CF pin by writing to this 12-bit read/write register—se
the Energy-to-Frequency Co
Channel 1 RMS Value (Current Channel).
Channel 2 RMS Value (Voltage Channel).
Channel 1 RMS Offset Corre
Channel 2 RMS Offset Correction Register.
Apparent Gain Register. Calibrate the apparent power calculation by
writing to this register. The calibration range is 50% of the nominal
scale real power. The resolut
Apparent Energy Divider Register. The internal apparent energy regist
is divided by the value of this register before being stored in the
VAENERGY register.
Line Cycle Energy Accumulation Mode
register is used during line cycle energy accumulation mode to s
number of half line cycles for energy accumulation—see the Line Cycle
Energy Accumulation Mode section.
Zero-Crossing Timeout. If no zero crossings are detected on Channel 2
within the time specified in this 12-bit register, the interrupt request lin
(IRQ) will be activated—see the Zero-Crossing Detection section.
Sag Line Cycle Register. This 8-bit register specifies the number of
consecutive line cycles below SAGLVL that is required on Channel 2
before th
section.
Sag Voltage Level. An 8-bit write to this register determines at what
signal level on Chan
remain low for the number of cycles specified in the SAGCYC register
before the SAG pin is activated—see the Line Voltage Sag Detection
section.
Channel 1 Peak Level Threshold (Current Channel). This register sets the
level of current peak detection. If the Channel 1 input exceeds this level,
the PKI flag in the status register is set.
Channel 2 Peak Level Threshold (Voltage Channel). This register sets the
level of voltage peak detection. If the Channel 2 input exceeds this level,
the PKV flag in the status register is set.
Channel 1 Peak Register. The maximum input value of the current
channel, since the last read of the register is stored in this register.
Same as Channel 1 peak register, except that the register contents are
reset to 0 after a read.
Channel 2 Peak Register. The maximum input value of the voltage
channel, since the last read of the register is stored in this register.
Same as Channel 2 peak register, except that the register contents ar
reset to 0 after a read.
Temperature Register. This is an 8-bit register that contains the result of
the latest temperature conversion—see the Temperature Measurement
section.
ency Divider Denominator Register. Adjust the output
e SAG output is activated—see the Line Voltage Sag Detection
ll-scale active power. The resolution of the gain adjust is
nel 2 the SAG
ction Register.
nversion section.
ion of the gain adjust is 0.02444%/LSB.
pin becomes active. The signal must
Line-Cycle Register. This 16-bit
just the output frequency
et the
full-
peak
e
GY
er
e
e