ADE7763ARS Analog Devices Inc, ADE7763ARS Datasheet - Page 52

• Manufacturer Part Number: ADE7763ARS
• Description: IC ENERGY METER 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7763ARS

• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7763ZEB - BOARD EVALUATION FOR ADE7763
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADE7763
INTERRU
RESET IN
INTER
The status register is used by the MCU to
corresponding flag in the interrupt status gister is set to logic hig
the IRQ
register to determine the source of the int
T
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
able 12.
RUP
(CHANNEL 2 SAMPLE ABOVE VPKLVL)
logic output will go active low. W
(CHANNEL 1 SAMPLE ABOVE IPKLVL)
P
T
(POWER POSITIVE TO NEGATIVE)
(POWER NEGATIVE TO POSITIVE)
ERRUPT S
T STATUS
T ENABLE EGI
Interrupt
Flag
AEHF
SAG
CYCEND
WSMP
ZX
TEMP
RESET
AEOF
PKV
PKI
VAEHF
VAEOF
ZXTO
PPOS
PNEG
RESERVED
(ZERO-CROSSING TIMEOUT)
(VAENERGY IS HALF FULL)
(VAENERGY OVERFLOW)
TA
R
R
EGISTER
Description
Indicates that an interrupt occurred because the active energy register, AENERGY, is more than half full.
Indicates that an interrupt was caused by a sag on the line voltage.
Indicates the end of energy accumulation over an integral number of half line cycles, as defined by the content
of the LINECYC register—see the Line Cycle Energy Accumulation Mode section.
Indicates that new data is present in the waveform register.
This status bit reflects the status of the ZX logic ouput—see the Zero-Crossing Detection section.
Indicates that a temperature conversion result is available in the temperature register.
Indicates the end of a reset for software and hardware resets. The corresponding enable bit has no function in
the interrupt enable register, i.e., this status bit is set at the end of a reset, but cannot be enabled to cause an
interrupt.
Indicates that the active energy register has overflowed.
Indicates that the waveform sample from Channel 2 has exceeded the VPKLVL value.
Indicates that the waveform sample from Channel 1 has exceeded the IPKLVL value.
Indicates that an interrupt occurred because the apparent energy register, VAENERGY, is more than half full.
Indicates that the apparent energy register has overflowed.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage for a specified number of
line cycles—see the Zero-Crossing Timeout section.
Indicates that the power has gone from negative to positive.
Indicates that the power has gone from positive to negative.
Reserved.
TUS R
RESERVED
STER (0
VAEOF
VAEHF
PNEG
PPOS
ZXTO
PKV
PKI
EGI
(0
STER (0x0C)
err
x0B),
x0A)
re
hen
determine the
15 14 13 12 11 10
0
upt.
the MCU services th
0
Figure 87. Interrupt Status/Interrupt Enable Register
0
0
0
,
source of a
0
Rev. A | Page 52 of 56
9
0
8
0
h. I
e in
n interr
7
0
f the enable bi
terrupt, it mu
6
0
5
0
upt requ
4
0
3
0
2
0
t for this fla
est ( IRQ ). When an interrupt event occurs, the
st first carry out a
1
0
0
0
ADDR: 0x0A, 0x0B, 0x0C
AEHF
(ACTIVE ENERGY HALF FULL)
SAG
(SAG ONLINE VOLTAGE)
CYCEND
(END OF LINECYC HALF LINE CYCLES)
WSMP
(WAVEFORM SAMPLES DATA READY)
ZX
(ZERO CROSSING)
TEMP
(TEMPERATURE DATA READY)
RESET
(END OF SOFTWARE/HARDWARE RESET)
AEOF
(ACTIVE ENERGY REGISTER OVERFLOW)
g is Logic 1 in the interrupt enable register,
read from the interrupt status