ADE7763ARS Analog Devices Inc, ADE7763ARS Datasheet - Page 50

• Manufacturer Part Number: ADE7763ARS
• Description: IC ENERGY METER 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7763ARS

• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7763ZEB - BOARD EVALUATION FOR ADE7763
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADE7763
REGISTER DESCRIPTIONS
All ADE7763 functionality is accessed via on-chip registers. Each r
then tr
COM
The c
processor. All data transfer operations must begin with a write to t
registe
designations for the communication register.
DB7
W/R
Table 10. Communication Register
Bit
Location
0 to 5
6
7
MODE REGISTER (0x09)
The ADE7763 functionality is configured by writing to the mode register. Table 11 describes the functionality of each bit
in the register.
Table 11.
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
12, 11
omm
MU
r det
ansf ring the regis
er
NICATIO
unication r
ermines
Bit
Mnemonic
A0 to A5
RESERVED
W/R
Bit
Mnemonic
DISHPF
DISLPF2
DISCF
DISSAG
ASUSPEND
TEMPSEL
SWRST
CYCMODE
DISCH1
DISCH2
SWAP
DTRT1, 0
DB6
0
wheth the n t operation is a read o
N R
egis
ter
ter
EGIS ER
er
Description
The 6 LSBs of the communication register specify the register for the data transfer operation. Table 9 lists the
address of each on-chip register.
This bit is unused and should be set to 0.
When this bit is a Logic 1, the data transfer operation immediately following the write to the communication
register is interpreted as a write to the ADE7763. When this bit is a Logic 0, the data transfer operation
immediately following the write to the communication register is interpreted as a read operation.
Default
Value
0
0
1
1
0
0
0
0
0
0
0
00
data.
is an
T
A
ex
8-
DB5
A5
full descr tion of the se
bit, write
Description
HPF (high-pass filter) in Channel 1 is disabled when this bit is set.
LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.
Frequency output CF is disabled when this bit is set.
Line voltage sag detection is disabled when this bit is set.
By setting this bit to Logic 1, both A/D converters can be turned off. During normal operation, this
bit should be left at Logic 0. All digital functionality can be stopped by suspending the clock
signal at CLKIN pin.
Temperature conversion starts when this bit is set to 1. This bit is automatically reset to 0 after the
temperature conversion.
Software Chip Reset. A data transfer should not take place to the ADE7763 for at least 18 µs after
a software reset.
Setting this bit to Logic 1 places the chip in line cycle energy accumulation mode.
ADC 1 (Channel 1) inputs are internally shorted together.
ADC 2 (Channel 2) inputs are internally shorted together.
By setting this bit to Logic 1, the analog inputs V2P and V2N are connected to ADC 1 and the
analog inputs V1P and V1N are connected to ADC 2.
Use these bits to select the waveform register update rate.
DTRT1
0
0
1
1
ip
-only
regist
DB4
A4
er th
r a
ria
Rev. A | Page 50 of 56
write
at con
l int
he communication register. The data written to the communication
DTRT0
0
1
0
1
egister is accessed by first writing to the communication reg
erface proto
and which register is being accessed. Table 10 outlines the bit
trols the serial data transfer between the ADE7763 and the host
DB3
A3
col is given in the Serial Interface section.
Update Rate
27.9 kSPS (CLKIN/128)
14 kSPS (CLKIN/256)
7 kSPS (CLKIN/512)
3.5 kSPS (CLKIN/1024)
DB2
A2
A1
DB1
DB0
A0
ister and