LT4220CGN Linear Technology, LT4220CGN Datasheet - Page 12

• Manufacturer Part Number: LT4220CGN
• Description: IC CNTRLR DUAL HOT SWAP 16-SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LT4220CGN

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.7 V ~ 16.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LT4220
APPLICATIO S I FOR ATIO
Whenever the output voltages reach their final value as
sensed by R9, R10 and R11, R12 and both gate signals are
fully on, the PWRGD pin will go high impedance.
A typical timing sequence is shown in Figure 8 with
tracking enabled. The sequence is as follows:
1) The power pins make contact and the undervoltage
2) The ON comparator thresholds are exceeded and the
3) GATE
4) When the magnitude of V
5) GATE
6) GATE
12
lockout thresholds are exceeded.
GATE pins start ramping up. V
the N-channel FET threshold voltage.
lags behind V
holds at approximately the threshold voltage of the
N-channel FET due to C2 slew rate control.
GATE
the faster V
enabling the FB output comparators. If both FB com-
+
+
+
–
is limited by the tracking circuit because V
internal gate good signal threshold is reached.
resumes ramping. The slowest V
internal gate good signal threshold is reached,
PWRGD
GATE
GATE
V
V
Figure 8. Typical Timing Sequence
OUT +
OUT –
ON
ON
V
OUT
V
CC
EE
+
–
+
–
OUT
slew rate.
U
+
. When V
1 2
+UVLO
–UVLO
3 4
U
OUT
OUT
–
–
OUT
catches up with V
starts ramping, GATE
W
5
+ follows GATE
6
4220 F08
OUT
U
will limit
OUT
OUT
+
by
+
–
–
,
Power Supply Ramping
For large capacitive loads, the inrush current will be limited
by the V
current limit. For a desired inrush current that is less than
the fold-back current limit, the feedback networks R6, C1
and R8, C2 can be used to control the V
the desired inrush current and typical gate pull-up current,
the feedback network capacitors C1 and C2 can be calcu-
lated as:
where CL1 and CL2 are the positive and negative output
load capacitance. If the supply-tracking mode is enabled
(TRACK = High), during startup, the output with the
slowest slew rate will also limit the slew rate of the
opposite output (Note: Supply-tracking is also controlled
by the resistive dividers on the FB pins. See Supply
Tracking). Additionally, C1 and C2 should be greater than
5nF to prevent large overshoot in the output voltage for
transient loads with small capacitive loads.
Capacitor C3 and resistor R8 prevent Q2 from momen-
tarily turning on when the power pins first make contact.
Without C3, capacitor C2 and C
of Q2 near ground before the LT4220 could power up and
pull the gate low. The minimum required value of C3 can
be calculated by:
where V
V
C2 is not used, the minimum value for C3 should be 10nF
to ensure stability. C2 and C3 must be the same type to
ensure tracking over temperature.
EEMAX
C1 = (10 A • CL1)/I
C2 = (10 A • CL2)/I
parators indicate the output is good, the PWRGD pin
output goes high impedance and is pulled up by an
external pullup resistor.
C
3
is the maximum negative supply input voltage. If
TH
OUT
V
is the MOSFET’s minimum gate threshold and
EE
+
V
and V
TH
V
TH
OUT
(
C
INRUSH
INRUSH
GD Q
–
(
slew rate or by the fold-back
2
+
–
)
GD(Q2)
and
C
2
) • .
would hold the gate
1 2
OUT
slew rate. For
4220f
(1)
(3)
(2)