A6281EESTR-T Allegro Microsystems Inc, A6281EESTR-T Datasheet - Page 3

• Manufacturer Part Number: A6281EESTR-T
• Description: IC LED DRIVER PWM CONTROL 16-QFN
• Manufacturer: Allegro Microsystems Inc
• Type: PWM Controlr

Specifications of A6281EESTR-T

• Topology: Linear, PWM
• Constant Current: Yes
• Number Of Outputs: 3
• Internal Driver: Yes
• Type - Secondary: RGB
• Frequency: 5MHz
• Voltage - Supply: 4.75 V ~ 17 V
• Voltage - Output: 1 V ~ 3 V
• Mounting Type: Surface Mount
• Package / Case: 16-WFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 150mA
• Internal Switch(s): Yes
• Led Driver Application: Architectural Lighting, Displays
• No. Of Outputs: 3
• Output Current: 165mA
• Output Voltage: 3V
• Input Voltage: 4.75V To 17V
• Operating Supply Voltage (typ): 5/9/12/15V
• Number Of Segments: 3
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: QFN EP
• Pin Count: 16
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 17V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 620-1218-2

A6281
Terminal List Table
Number
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
–
R
EXT
VREG
REXT
PGND
Name
VREG
LGND
REXT
OUT2
OUT1
OUT0
SDI
OEI
VIN
SDO
OEO
PAD
VIN
OEI
SDI
CO
LO
CI
LI
CI
LI
Regulator
800 kHz Clock
An external resistor at this terminal establishes maximum output current
Regulator decoupling
Logic ground
Chip power supply voltage; connect to VREG externally if 4.75 V < V
Serial clock input; PWM clock if external clock is selected
Output enable input; when low (active), the output drivers are enabled; when high (inactive), all
output drivers are turned off (blanked)
Latch input terminal; serial data is latched with high-level input
Serial data input to shift register
Sinking output terminal
Power ground
Sinking output terminal
Sinking output terminal
Buffered serial data output after shift register
Buffered latch output
Buffered output enable output
Buffered clock output
Exposed thermal pad, not internally connected; connect externally to LGND and PGND.
To PWM Counters
To logic
To PWM Counters
Regulator 0
Current
3-Channel Constant Current LED Driver
Functional Block Diagram
OUT0
VREG
LGND
REXT
VIN
Pin-out Drawings
1
2
3
4
Latched Registers
with Programmable PWM Control
Shift Register
PAD
Regulator 1
Current
OUT1
12
10
11
9
Description
OUT0
OUT1
PGND
OUT2
Regulator 2
Current
One-Shot
100 ns
OUT2
IN
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
< 5.5 V
PGND
LGND
SDO
CO
LO
OEO
3