A6281EESTR-T Allegro Microsystems Inc, A6281EESTR-T Datasheet - Page 6

• Manufacturer Part Number: A6281EESTR-T
• Description: IC LED DRIVER PWM CONTROL 16-QFN
• Manufacturer: Allegro Microsystems Inc
• Type: PWM Controlr

Specifications of A6281EESTR-T

• Topology: Linear, PWM
• Constant Current: Yes
• Number Of Outputs: 3
• Internal Driver: Yes
• Type - Secondary: RGB
• Frequency: 5MHz
• Voltage - Supply: 4.75 V ~ 17 V
• Voltage - Output: 1 V ~ 3 V
• Mounting Type: Surface Mount
• Package / Case: 16-WFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 150mA
• Internal Switch(s): Yes
• Led Driver Application: Architectural Lighting, Displays
• No. Of Outputs: 3
• Output Current: 165mA
• Output Voltage: 3V
• Input Voltage: 4.75V To 17V
• Operating Supply Voltage (typ): 5/9/12/15V
• Number Of Segments: 3
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: QFN EP
• Pin Count: 16
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 17V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 620-1218-2

A6281
Shift Register
The A6281 has a 32-bit shift register that loads data through the
SDI (serial data in) pin. The shift register operates by a first-in
first-out (FIFO) method. The most significant bit (MSB, bit 31)
is the first bit shifted in and the least significant bit (LSB, bit 0)
is shifted in last. The serial data is clocked by a rising edge of the
CI (clock in) pin. The SDO (serial data out) pin is updated to the
state of bit 31 on the falling edge of the CI pin. This will prevent
any race conditions and erroneous data that might occur while
propagating information through multiple A6281s that are daisy
chained together. The contents of the shift register will continue
to propagate on every rising edge of the CI pin. The information
in the shift register is latched on a low-to-high transition of the LI
(Latch In) pin. The LI pin must be brought low before the rising
edge of the next clock pulse, to avoid latching erroneous data.
The latched data remains latched on a rising signal on the OEI
(output enable in) pin.
Output Buffers
The A6281 is designed to allow daisy chaining many A6281s
together. It can pass the clock, data, latch, and output enable
signals from one A6821 to the next without any loss of data due
to duty cycle skewing or signal degradation.
The A6821 is equipped with output buffers that allow the data
signals to travel over long distances through strings of A6281s
without the need for extra driving hardware. The A6281 drives
R
EXT
Figure 4. Functional Diagram
VREG
REXT
OEI
SDI
VIN
CI
LI
800 kHz
Regulator
+5V
Scalar 0
Shift Register
Latched Registers
Current
0 to 6
7 Bits
PWM Counter 0
Regulator 0
Current
10 Bits
Clock
Mode
2 Bits
7 to 8
OUT0
Functional Description
3-Channel Constant Current LED Driver
Unused
1 Bit
9
Scalar 1
10 to 16
Current
7 Bits
PWM Counter 1
Regulator 1
Current
with Programmable PWM Control
10 Bits
OUT1
these signals to TTL levels. Each of the A6281 inputs has a cor-
responding buffered output:
• CI (clock in) pin to CO (clock out) pin
• LI (latch in) pin to LO (latch out) pin
• OEI (output enable in) pin to OEO (output enable out) pin
• SDI (serial data in) pin to SDO (serial data out) pin
The CO (clock out) pin is driven by an internal one-shot circuit.
When the CI pin detects an edge rising through the input thresh-
old, the one-shot circuitry drives the CO pin high for 100 ns. The
CI pin input threshold has hysteresis to prevent false triggering
of the CO signal. The implementation of the one-shot solution
allows many A6281s to be daisy chained together with a consis-
tent clock signal throughout the entire chain without degradation
or loss of synchronicity to the data line.
The A6281 controls the intensity of each LED by pulse width
modulating the current of each output. The A6281 has three
10-bit brightness registers, one for each output. These brightness
registers set the PWM count value at which the outputs switch
off during each PWM cycle. Each 10-bit brightness register gives
1023 levels of light intensity. The duty cycle, DC, can be deter-
mined by the following equation:
where PWM
the brightness register.
Unused
17 to 19
PWM Brightness Control
3 Bits
Scalar 2
20 to 26
Current
7 Bits
PWM Counter 2
n
Regulator 2
DC = [(PWM
Unused
Current
is the PWM value greater than zero that is stored in
10 Bits
1 Bit
27
OUT2
28 to 29
Test
‘’00”
Bits
One-Shot
100 ns
Address
Address
PGND
Bit
Bit
“1”
“0”
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
n
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
30
+ 1) / 1024] ×100 (%) ,
Unused
Unused
LGND
1 Bit
1 Bit
31
SDO
CO
LO
OEO
6