A6281EESTR-T Allegro Microsystems Inc, A6281EESTR-T Datasheet - Page 7

• Manufacturer Part Number: A6281EESTR-T
• Description: IC LED DRIVER PWM CONTROL 16-QFN
• Manufacturer: Allegro Microsystems Inc
• Type: PWM Controlr

Specifications of A6281EESTR-T

• Topology: Linear, PWM
• Constant Current: Yes
• Number Of Outputs: 3
• Internal Driver: Yes
• Type - Secondary: RGB
• Frequency: 5MHz
• Voltage - Supply: 4.75 V ~ 17 V
• Voltage - Output: 1 V ~ 3 V
• Mounting Type: Surface Mount
• Package / Case: 16-WFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 150mA
• Internal Switch(s): Yes
• Led Driver Application: Architectural Lighting, Displays
• No. Of Outputs: 3
• Output Current: 165mA
• Output Voltage: 3V
• Input Voltage: 4.75V To 17V
• Operating Supply Voltage (typ): 5/9/12/15V
• Number Of Segments: 3
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: QFN EP
• Pin Count: 16
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 17V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 620-1218-2

A6281
The relationship of the PWM
given in the following table:
When the brightness register is set to zero, the outputs remain off
for the duration of the PWM cycle for a 0% DC. When a bright-
ness register is set to 1023, the LED for that output remains on
(100% DC) when OEI is active and begins the PWM cycle. The
output remains on when the PWM counter rolls over and begins
a new count.
The PWM counter begins counting at zero and increments only
when the OEI pin is held low. When the PWM counter reaches
the count of 1024, the counter resets to zero and continues
incrementing. The counter resets to zero on a rising edge of OEI,
upon recovery from UVLO, or when powering up. Latching new
data into the brightness registers will not reset the PWM counter.
A free-running internal 800 kHz oscillator is the master clock
for the PWM counter. A programmable clock divider frequency
allows the PWM to be set at approximately at 200 kHz, 400 kHz,
or 800 kHz, or the PWM can be set to count on the rising edge
of the external CI signal. Bit assignments for the programmable
clock divider are shown in the following table:
The total number of possible colors of an RGB pixel is over
1 billion. Refer to figure 4 for the mapping of shift register bits
to latches.
Figure 5. Register Configuration
a
c
0 1 2 3 4 5 6
Selects which word is written to: Dot Correction/Clock Mode selection or PWM counter.
Allegro Test Bit (ATB). Reserved for Allegro internal testing. Always set to zero (0) in the application.
7
0
1
0
1
Bits
Dot Correction
PWM
1023
Register 0
. . .
8
0
0
1
1
PWM Counter 0
0
1
2
n
External (count on rising
n
value to the output duty cycle is
1024/1024 (100 %)
edge of CI signal)
Clock Mode
Duty Cycle
7
Clock
Mode
0/1024 (0 %)
2/1024
3/1024
800 kHz
400 kHz
200 kHz
. . .
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
X
Dot Correction
Register 1
PWM Counter 1
3-Channel Constant Current LED Driver
Bits
with Programmable PWM Control
X X X
Output Current Selection
The overall maximum current is set by the external resistor,
R
being set, the maximum current remains constant regardless of
the LED voltage variation, supply voltage variation, temperature,
or other circuit parameters. The maximum output current can be
calculated using the following equation:
The relationship of the value selected for R
shown in figure 6.
Internal Linear Regulator
The A6281 has a built-in linear regulator. The regulator operates
from a supply voltage of 5.5 to 17 V. It allows the VIN pin of the
A6281 to connect to the same supply as the LEDs. This simpli-
fies board design by eliminating the need for a chip supply bus
and external voltage regulators. For 5 V supplies, connect VIN
to VREG externally. Note: When using 5 V supplies, ensure that
VIN does not exceed the absolute maximum rating of the VREG
pin (6 V).
The V REG pin is used by the internal linear regulator to connect
to a bypass capacitor. This pin is for internal use only and is not
EXT
150
140
130
120
110
100
Figure 6. Output Current versus External Resistor, R
90
80
70
60
50
40
30
20
10
0
, connected between the REXT and LGND pins. After
5
Dot Correction
Register 2
15
PWM Counter 2
I
OUT
b
25
X indicates
(max) = 753.12 / R
X ATB
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
R
35
28
EXT
“
c
Don’t Care.”
(kΩ)
ATB
29
45
c
Address “0” X
Address “1” X
EXT
30
EXT
55
a
.
and I
31
65
b
OUT
EXT
is
75
7