A6281EESTR-T Allegro Microsystems Inc, A6281EESTR-T Datasheet - Page 9

• Manufacturer Part Number: A6281EESTR-T
• Description: IC LED DRIVER PWM CONTROL 16-QFN
• Manufacturer: Allegro Microsystems Inc
• Type: PWM Controlr

Specifications of A6281EESTR-T

• Topology: Linear, PWM
• Constant Current: Yes
• Number Of Outputs: 3
• Internal Driver: Yes
• Type - Secondary: RGB
• Frequency: 5MHz
• Voltage - Supply: 4.75 V ~ 17 V
• Voltage - Output: 1 V ~ 3 V
• Mounting Type: Surface Mount
• Package / Case: 16-WFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 150mA
• Internal Switch(s): Yes
• Led Driver Application: Architectural Lighting, Displays
• No. Of Outputs: 3
• Output Current: 165mA
• Output Voltage: 3V
• Input Voltage: 4.75V To 17V
• Operating Supply Voltage (typ): 5/9/12/15V
• Number Of Segments: 3
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: QFN EP
• Pin Count: 16
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 17V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 620-1218-2

A6281
Timing Considerations
A6281s can be used in large numbers to drive many LEDs with
the control signals connected serially together using short cables
between each pixel (see figure 8). Because the clock negative
edge drives the data to the SDO pin, and the CO pin is driven
by a 100 ns one-shot function, the clock and data signals remain
synchronized with each other from the first pixel in the chain to
the last.
After all of the data is written to each A6281 in the chain, the
data is latched into each A6281 via a low-to-high transition on
the LI pin. The LO pin of pixel #1 drives the LI pin of pixel #2,
and so on down the chain. These signals are buffered and are
driven asynchronously relative to the CI and SDI pins. Therefore
the mismatch in delays between CO and LO must be taken into
consideration.
CO(n-1) = CI(n)
LO (n -1) = LI (n )
CO(1) = CI(2)
CO(2) = CI(3)
LO (1) = LI (2)
LO (2) = LI (3)
CI(1)
LI (1)
Figure 7. Signal Delay Mismatch Timing Diagram. t
applied to the first pixel in the chain. Note the difference in delay for CI(1) to CI(n) compared
to the delay for LI(1) to LI(n). This must be compensated by increasing t
Application Information
3-Channel Constant Current LED Driver
with Programmable PWM Control
Although the mismatches in delays are quite small, they must be
considered when creating the timing pattern for driving the chain.
The key parameter is the setup time from the last CI clock rising
edge to the rising edge of LI.
The minimum A6281 setup time from CI to LI is 20 ns. There
may be a 5 ns per pixel mismatch in the propagation delays of the
CI and LI signals (the delay from CI to CO compared to the delay
from LI to LO). As a rule of thumb, use a setup time, t
first A6281 in the chain as calculated below:
where n is the number of pixels in the chain.
This will ensure that the setup time at the last pixel in the chain is
at least 20 ns.
su
is the setup time for signals (CI to LI)
CI(1) to CI(n)
t
su
= 20 ns + n × 5 ns ,
t
su
su
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
.
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
LI(1) to LI(n)
su
, at the
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