LP5520TL/NOPB National Semiconductor, LP5520TL/NOPB Datasheet - Page 24

• Manufacturer Part Number: LP5520TL/NOPB
• Description: IC LED DRIVER RGB 25-USMD
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: RGB LED Driverr

Specifications of LP5520TL/NOPB

• Constant Current: Yes
• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 3
• Internal Driver: Yes
• Type - Primary: Backlight, Light Management Unit (LMU)
• Type - Secondary: RGB, White LED
• Frequency: 1.22kHz, 19.52kHz
• Voltage - Supply: 2.9 V ~ 5.5 V
• Voltage - Output: 5 V ~ 20 V
• Mounting Type: Surface Mount
• Package / Case: 25-MicroSMD
• Operating Temperature: -30°C ~ 85°C
• Current - Output / Channel: 60mA
• Internal Switch(s): Yes
• Efficiency: 87%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LP5520TLTR

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I
I
The serial interface is in I
pin is used for the I
rectional data transfer. Both these signals need a pull-up
resistor according to I
up resistors are determined by the capacitance of the bus
(typical resistance is 1.8k). Signal timing specifications are
shown in table I
I
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when CLK is LOW.
I
START and STOP bits classify the beginning and the end of
the I
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I
START and STOP bits. The I
after START condition and free after STOP condition. During
data transmission, I
conditions. First START and repeated START conditions are
equivalent, function-wise.
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 20h when SI=0 and 21h when SI=1 for LP5520.
2
2
2
2
C SIGNALS
C DATA VALIDITY
C START AND STOP CONDITIONS
C Compatible Interface
2
C session. START condition is defined as SDA signal
2
C Timing Parameters.
I
2
C Signals: Data Validity
2
2
C clock and the SDA pin is used for bidi-
C master can generate repeated START
2
C specification. The values of the pull-
2
C mode when IF_SEL = 0. The SCL
2
C bus is considered to be busy
2
C master always generates
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I
2
C Write Cycle
24
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
After the START condition, the I
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LP5520 address
is 20h when SI=0 and 21h when SI=1. For the eighth bit, a
“0” indicates a WRITE and a “1” indicates a READ. The sec-
ond byte selects the register to which the data will be written.
The third byte contains data to write to the selected register.
I
2
C Start and Stop Conditions
th
clock pulse, signifying an acknowledge. A
I
2
C Chip Address
2
C master sends a chip ad-
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