ISL6210CRZ Intersil, ISL6210CRZ Datasheet - Page 6

• Manufacturer Part Number: ISL6210CRZ
• Description: IC MOSFET DRIVER DUAL SYNC 16QFN
• Manufacturer: Intersil

Specifications of ISL6210CRZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 26ns
• Current - Peak: 2A
• Number Of Configurations: 2
• Number Of Outputs: 4
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Diagram
Description
Theory of Operation
Designed for speed, the ISL6210 dual MOSFET driver
controls both high-side and low-side N-Channel FETs for two
separate channels of a Multiphase PWM system from two
independent PWM signals.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see “Timing Diagram” on page 6). After a short
propagation delay [t
Typical fall times [t
Specifications” table on page 4. Adaptive shoot-through
circuitry monitors the LGATE voltage. When LGATE has
fallen below 1V, UGATE is allowed to turn ON. This prevents
both the lower and upper MOSFETs from conducting
simultaneously, or shoot-through.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
gate begins to fall [t
voltage is monitored, and the lower gate is allowed to rise
after the upper MOSFET gate-to-source voltage drops below
1V. The lower gate then rises [t
MOSFET.
This driver is optimized for converters with large step down
compared to the upper MOSFET because the lower
MOSFET conducts for a much longer time in a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement.
The 0.5Ω ON-resistance and 4A sink current capability
enable the lower gate driver to absorb the current injected to
the lower gate through the drain-to-gate capacitor of the
PWM
UGATE
LGATE
t
PDLL
t
FL
PDHU
FU
PDLL
PDLU
1V
] are provided in the “Electrical
]. The upper MOSFET gate-to-source
t
], the lower gate begins to fall.
] is encountered before the upper
RU
6
RL
t
PDLU
], turning on the lower
t
PDHL
1V
FIGURE 1. TIMING DIAGRAM
2.5V
t
RL
ISL6210
t
FL
lower MOSFET and prevent a shoot through caused by the
high dv/dt of the phase node.
Diode Emulation
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6210 will detect the zero current crossing of the output
inductor and turn off LGATE. This ensures that
discontinuous conduction mode (DCM) is achieved. Diode
emulation is asynchronous to the PWM signal. Therefore,
the ISL6210 will respond to the FCCM input immediately
after it changes state.
Please note that Intersil does not recommend Diode
Emulation use with r
turn-OFF of the low side MOSFET can cause gross current
measurement inaccuracies.
Three-State PWM Input
A unique feature of the ISL6210 and other Intersil drivers is the
addition of a shutdown window to the PWM input. If the PWM
signal enters and remains within the shutdown window for a set
holdoff time, the output drivers are disabled and both MOSFET
gates are pulled and held low. The shutdown state is removed
when the PWM signal moves outside the shutdown window.
Otherwise, the PWM rising and falling thresholds outlined in the
“Electrical Specifications” table on page 4 determine when the
lower and upper gates are enabled.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to turn on.
t
TSSHD
t
PTS
t
RU
t
TSSHD
DS(ON)
current sensing topologies. The
t
FU
t
PTS
December 9, 2008
FN6392.1