MCZ33927EKR2 Freescale Semiconductor, MCZ33927EKR2 Datasheet - Page 31
![IC FET PRE-DRIVER 3PH 54-SOIC](/photos/15/90/159027/soic-54_sml.jpg)
MCZ33927EKR2
Manufacturer Part Number
MCZ33927EKR2
Description
IC FET PRE-DRIVER 3PH 54-SOIC
Manufacturer
Freescale Semiconductor
Specifications of MCZ33927EKR2
Configuration
3 Phase Bridge
Input Type
Inverting and Non-Inverting
Delay Time
265ns
Current - Peak
600mA
Number Of Configurations
1
Number Of Outputs
3
High Side Voltage - Max (bootstrap)
75V
Voltage - Supply
8 V ~ 40 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 11. Setting Interrupt Masks
MODE COMMAND
Table 12. MODE Command
Analog Integrated Circuit Device Data
Freescale Semiconductor
MASK0:0
MASK0:1
MASK0:2
MASK0:3
MASK1:0
MASK1:1
MASK1:2
MASK1:3
SPI Data Bits
Write
Reset
Sending a MODE command and setting the Mode Lock simultaneously are allowed. This sets the requested mode and locks out any further
changes.
This command is sent by sending binary 010x xxxx data.
• Bit 0 – Mode Lock is used to enable or disable Mode Lock. If Bit 0 is set, changes to the internal registers are disallowed
• Bit 1 – FULLON Mode. If this bit is set, programmed deadtime control is disabled, making it is possible to have both high-
• Bit 3 – Desaturation Fault Mode controls what happen when a desaturation event is detected. When set to “0”, any
Mask:bit
to prevent inadvertent changes. This bit cannot be cleared once set. Since the mode Lock mode can only be set, this bit
prevents any subsequent, and likely erroneous, mode, deadtime, or mask register changes from being received. The only
way to clear this bit is to RESET the IC. If an attempt is made to write to a register when Mode Lock is enabled, a Write
Error fault is generated.
and low-side drivers in a phase on simultaneously. This could be useful in special applications such as alternator
regulators, or switched-reluctance motor drive applications. There is no deadtime control in FULLON mode. Input signals
directly control the output stages, synchronized with the internal clock.
This bit is a “0”, after RESET. Until overwritten, the IC operates normally; deadtime control and logic prevents both outputs
from being turned on simultaneously.
desaturation on any channel causes all six output drivers to shutoff. The drivers can only be re-enabled by executing the
CLINT command. When 1, desaturation faults are completely ignored.
Bit 3 controls behavior if a Desaturation, or Phase Error event is detected. The possibilities are:
— 0: Default: When a Desaturation, or Phase Error event is detected on any channel, all channels turn off and generates
an Interrupt, if interrupts are enabled.
— 1: Disable: Desaturation /Phase Error channel shutdown is disabled, but interrupts are still possible if unmasked.
Overtemperature on any gate drive output generates an interrupt if this bit is set.
Desaturation event on any output generates an interrupt if this bit is set.
VLS undervoltage generates an interrupt if this bit is set.
Overcurrent Error–if the overcurrent comparator threshold is exceeded, an interrupt is generated.
Phase Error–if any Phase comparator output is not at the expected value when an output is command on, an interrupt is
generated. This signal is the XOR of the phase comparator output with the output drive state, and blacked for the duration
of the desaturation blanking interval.
In FULLON mode, this signal is blanked and cannot generate an error.
Framing Error–if a framing error occurs, an interrupt is generated.
Write Error after locking.
Reset Event–If the IC is set or disabled, an interrupt occurs. Since the IC will always start from a reset condition, this can be
used to test the interrupt mechanism because when the IC comes out of RESET, an interrupt will immediately occur.
7
0
6
1
5
0
4
0
Description
Desaturation
Fault Mode
3
0
LOGIC COMMANDS AND REGISTERS
2
0
0
FUNCTIONAL DEVICE OPERATION
FULLON
Mode
1
0
Mode
Lock
0
0
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