MCZ33927EK Freescale Semiconductor, MCZ33927EK Datasheet - Page 33

• Manufacturer Part Number: MCZ33927EK
• Description: IC FET PRE-DRIVER 3PH 54-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33927EK

• Configuration: 3 Phase Bridge
• Input Type: Inverting and Non-Inverting
• Delay Time: 265ns
• Current - Peak: 600mA
• Number Of Configurations: 1
• Number Of Outputs: 3
• High Side Voltage - Max (bootstrap): 75V
• Voltage - Supply: 8 V ~ 40 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STATUS REGISTERS
the return value from the SPI port. There are four variants of
the NULL command used to read various status in the IC.
Status Register 0 (Status Latch Bits)
returns the following data:
Table 14. Status Register 0
Analog Integrated Circuit Device Data
Freescale Semiconductor
set. If the status is still present, that bit will not clear. CLINT0 and CLINT1 have the same format as MASK0 and MASK1
respectively.
SPI Data Bits
Results
Register 0
Read
Reset
After any SPI command, the status of the IC is reported in
This register is read by sending the NULL0 command (000x xx00). It is also returned after any other command. This command
All status bits are latched. The latches are cleared only by sending a CLINT0 or CLINT1 command with the appropriate bits
• Bit 0 –is a flag for Overtemperature on any channel. This bit is the OR of the latched three internal TLIM detectors.This
• Bit 1 –is a flag for Desaturation Detection on any channel. This bit is the OR of the latched three internal high-side
• Bit 2 – is a flag for Low Supply Voltage . This bit is latched, thus a prior low voltage event is returned once before being
• Bit 3 –is a flag for the output of the Overcurrent Comparator . This flag can generate an interrupt if the appropriate mask
• Bit 4 –is a flag for a Phase Error . If any Phase comparator output is not at the expected value when just one of the
• Bit 5 –is a flag for a Framing Error . A framing error is a SPI message not a multiple of eight bits (a 0-length message is
• Bit 6 –indicates a Write Error After the Lock bit is set. A write error is any attempted write to the MASKn, Mode, or a
• Bit 7 –is set upon exiting RST . It can be used to test the interrupt mechanism or to flag for a condition where the IC gets
flag can generate an interrupt if the appropriate mask bit is set.
desaturation detectors and phase error logic. Faults are also detected on the low-side as phase errors. A phase error is
generated if the output signal (at Px_HS_S) does not properly reflect the drive conditions. The phase error is the triple OR
of phase errors from each phase. Each phase error is the OR of the HS and LS phase errors. An HS phase error (which
will also trigger the desaturation detector) occurs when the HS FET is commanded on, and the Px_HS_S is still low in the
deadtime duration after it is driven ON. Similarly, a LS phase error occurs when the LS FET is commanded on, and the
Px_HS_S is still high in the deadtime duration after the FET is driven ON. This flag can generate an interrupt if the
appropriate mask bit is set.
cleared on read. This flag can generate an interrupt if the appropriate mask bit is set.
bit is set.
individual high- or low-side outputs is enabled, the fault flag is set. This signal is the XOR of the phase comparator output
with the output driver state, and blanked for the duration of the desaturation blanking interval. This flag can generate an
interrupt if the appropriate mask bit is set.
also a framing error), or SI, or SCLK toggling detected while measuring the Deadtime calibration pulse. This would typically
be a transient or permanent hardware error, perhaps due to noise on the SPI lines. This flag can generate an interrupt if
the appropriate mask bit is set.
Deadtime command after the Mode Lock bit is set. A write error is any attempt to write any other command than the one
defined in the
bit is set.
reset without the host being otherwise aware. This flag can generate an interrupt if the appropriate mask bit is set.
Table
RESET
Event
7
1
7. This would typically be a software error. This flag can generate an interrupt if the appropriate mask
Write
Error
6
0
Framing
Error
5
0
Phase
Error
4
0
Other commands return a general status word in the Status
Register 0.
Register 0 is most commonly used for general status.
Registers one through three are used to read or confirm
internal IC settings.
There are four Status Registers in the IC. Status
Overcurrent
3
0
LOGIC COMMANDS AND REGISTERS
VLS
Low
2
0
FUNCTIONAL DEVICE OPERATION
any Channel
Detected on
DESAT
1
0
any Channel
Detected on
TLIM
0
0
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