AMIS30624C6245RG ON Semiconductor, AMIS30624C6245RG Datasheet - Page 23
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AMIS30624C6245RG
Manufacturer Part Number
AMIS30624C6245RG
Description
IC STEPPER DVR I2C 800MA 32-NQFP
Manufacturer
ON Semiconductor
Type
I2C Micro Stepping Motor Driverr
Datasheet
1.AMIS30624C6244RG.pdf
(56 pages)
Specifications of AMIS30624C6245RG
Applications
Stepper Motor Driver, 2 Phase
Number Of Outputs
1
Current - Output
800mA
Voltage - Supply
8 V ~ 29 V
Operating Temperature
-40°C ~ 165°C
Mounting Type
Surface Mount
Package / Case
32-VSQFP
Product
Stepper Motor Controllers / Drivers
Operating Supply Voltage
8 V to 29 V
Supply Current
800 mA
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Load
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
766-1002-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
ON Semiconductor
Quantity:
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AMIS30624C6245RG
Manufacturer:
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Part Number:
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AMIS-30624
14.2.6. Battery Under-voltage Management
The AMIS-30624 monitors the battery voltage by means of one threshold and one shutdown level, as illustrated in Figure 16. The only
condition necessary to reset flags <UV2> and <StepLoss> is to recover a battery voltage higher than UV1 and to receive a
GetFullStatus1
14.2.7. OTP Register
14.2.7.1 OTP Memory Structure
Table 16 shows where the parameters to be stored in the OTP memory are located.
Table 16: OTP Memory Structure
Parameters stored at address 0x00 and 0x01 and bit LOCKBT are already programmed in the OTP memory at circuit delivery. They
correspond to the calibration of the circuit and are just documented here as an indication.
Each OPT bit is at ‘0’ when not zapped. Zapping a bit will set it to ‘1’. Thus only bits having to be at ‘1’ must be zapped. Zapping of a bit
already at ‘1’ is disabled.
Each OTP byte will be programmed separately (see command SetOTPparam).
Once OTP programming is completed, bit LOCKBG can be zapped, to disable future zapping, otherwise any OTP bit at ‘0’ could still be
zapped by using a
Table 17: OTP Overwrite Protection
Note:
Zapped bits will really be “active” after a
Lock Bit
LOCKBT
LOCKBG
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
(factory zapped before delivery)
SecPos10
AbsThr3
SecPos7
DelThr3
Irun3
Vmax3
SetOTPparam
OSC3
Bit 7
command.
- <UV2> = '1'
- <Steploss> = '0'
- Motor Shutdown
GetOTPparam
AbsThr2
SecPos9
SecPos6
DelThr2
Irun2
Vmax2
OSC2
TSD2
command.
Bit 6
MODE
STOP
or a
Figure 16: State Diagram Battery Voltage Management
2
<GetFullStatus1>
ResetToDefault
AbsThr1
SecPos8
SecPos5
DelThr1
& I
Vbb > UV1
Irun1
Vmax1
OSC1
TSD1
Bit 5
Rev. 4 | Page 23 of 56 | www.onsemi.com
2
C frame
- <UV2> = '0'
- <Steploss> = '0'
Vbb < UV2
No Motion
command or after a power-up.
AbsThr0
SecPos4
DelThr0
Irun0
Vmax0
Shaft
OSC0
TSD0
Bit 4
VOLTAGE
NORMAL
& Motion Ongoing
Vbb < UV2
- <UV2> = '1'
- <Steploss> = '1'
- HardStop
- Motor Shutdown
StepMode1
SecPos3
Ihold3
IREF3
Vmin3
Protected Bytes
0x00 to 0x01
0x00 to 0x07
Acc3
Bit 3
BG3
PA3
<GetFullStatus1>
& I
Vbb > UV1
2
C frame
MODE
STOP
StepMode0
SecPos2
1
Ihold2
IREF2
Vmin2
Acc2
Bit 2
BG2
PA2
PC20060926.5
Ihold1
LOCKBT
IREF1
Vmin1
Acc1
Bit 1
BG1
PA1
Ihold0
LOCKBG
IREF0
Vmin0
Acc0
Bit 0
BG0
PA0