MC15XS3400CPNAR2 Freescale Semiconductor, MC15XS3400CPNAR2 Datasheet - Page 19

• Manufacturer Part Number: MC15XS3400CPNAR2
• Description: IC SWITCH HIGH SIDE QUAD 24-QFN
• Manufacturer: Freescale Semiconductor
• Type: High Side Switchr

Specifications of MC15XS3400CPNAR2

• Number Of Outputs: 4
• Rds (on): 15 mOhm
• Internal Switch(s): Yes
• Current Limit: 5A
• Voltage - Input: 6 ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. Dynamic Electrical Characteristics (continued)
otherwise noted. Typical values noted reflect the approximate parameter means at T
otherwise noted.
SPI INTERFACE CHARACTERISTICS
Notes
Analog Integrated Circuit Device Data
Freescale Semiconductor
Maximum Frequency of SPI Operation
Required Low State Duration for
Rising Edge of
Rising Edge of
Falling Edge of
Required High State Duration of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup Time)
SO Rise Time
SO Fall Time
SI,
SI,
Time from Rising Edge of
Time from Rising Edge of
37.
38.
39.
40.
41.
42.
Characteristics noted under conditions 6.0 V ≤ V
C
C
CS
CS
L
L
, SCLK, Incoming Signal Rise Time
, SCLK, Incoming Signal Fall Time
= 80 pF
= 80 pF
Parameters guaranteed by design.
RST
Maximum setup time required for the 15XS3400 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI,
Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on
Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on
low duration measured with outputs enabled and going to OFF or disabled condition.
CS
RST
CS
to Falling Edge of
to Rising Edge of SCLK (Required Setup Time)
to Falling Edge of
SCLK
SCLK
Characteristic
to SO Low-impedance
to SO High-impedance
RST
CS
(38)
(37)
CS
CS
CS
(Required Setup Time)
(40)
(40)
(Required Setup Time)
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
(Required Setup Time)
(40)
(40)
(41)
(42)
PWR
≤ 20 V, 3.0 V ≤ V
(39)
(39)
(39)
(39)
(39)
(39)
DD
t
t
Symbol
t
t
SI (HOLD)
t
WSCLKh
t
t
WSCLKl
SO(DIS)
t
SO(EN)
t
SI (SU)
t
WRST
t
t
f
LEAD
t
ENBL
t
t
RSO
LAG
FSO
≤ 5.5 V, - 40°C ≤ T
SPI
RSI
FSI
CS
CS
.
A
CS
DYNAMIC ELECTRICAL CHARACTERISTICS
= 25°C under nominal conditions, unless
Min
.
10
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A
ELECTRICAL CHARACTERISTICS
≤ 125°C, GND = 0 V, unless
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
500
8.0
1.0
5.0
50
50
60
37
49
13
13
13
13
60
60
–
15XS3400
Unit
MHz
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19