MC15XS3400CPNAR2 Freescale Semiconductor, MC15XS3400CPNAR2 Datasheet - Page 38

• Manufacturer Part Number: MC15XS3400CPNAR2
• Description: IC SWITCH HIGH SIDE QUAD 24-QFN
• Manufacturer: Freescale Semiconductor
• Type: High Side Switchr

Specifications of MC15XS3400CPNAR2

• Number Of Outputs: 4
• Rds (on): 15 mOhm
• Internal Switch(s): Yes
• Current Limit: 5A
• Voltage - Input: 6 ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDRESS 00101 — GLOBAL CONFIGURATION
REGISTER (GCR)
through the SPI.
detector. A logic [1] on VDD_FAIL_en bit allows transitioning
to Fail-safe mode for V
module. A logic [1] on PWM_en bit allows control of the
outputs HS[0:3] with PWMR register (the direct input states
are ignored).
reference by PWM module, as described in the following
Table
feedback on CSNS output pin, as shown in
38
15XS3400
Table 21. CSNS Reporting Selection
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 22. Output Current Recopy Selection
Table 19. Over-current Mode Selection
TEMP_en
Table 20. PWM Module Selection
OC_mode_s (D0)
CSNS1 (D3)
PWM_en (D7) CLOCK_sel (D6)
The GCR register allows the MCU to configure the device
Bit D8 allows the MCU to enable or disable the V
Bit D7 allows the MCU to enable or disable the PWM
Bit D6 (CLOCK_sel) allows to select the clock used as
Bits D5:D4 allow the MCU to select one of two analog
(D5)
X
0
1
20.
0
0
1
1
0
1
1
0
1
CSNS_en
(D4)
CSNS0 (D2)
0
1
0
inrush current and bulb cooling management
0
1
0
1
only inrush current management (default)
current recopy of selected output (D3:2] bits)
DD
X
0
1
< V
temperature on GND flag
DD(FAIL).
CSNS tri-stated (default)
Over-current Mode
CSNS reporting
PWM module enabled with
PWM module enabled with
internal calibrated clock
external clock from IN0
PWM module disabled
CSNS reporting
HS0 (default)
PWM module
HS1
HS2
HS3
(default)
Table
21.
DD
failure
(D0). When this bits is [0], the over-voltage is enabled (default
value).
ADDRESS 00111 — CALIBRATION REGISTER
(CALR)
clock, as explained in
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN DATA)
loaded. Meanwhile, the data is clocked out MSB- (OD15-)
first as the new message data is clocked into the SI pin. The
first sixteen bits of data clocking out of the SO, and following
a
word.
first 16 bits will be representative of the initial message bits
clocked into the SI pin since the
logic [0]. This feature is useful for daisy-chaining devices as
well as message verification.
transition of [0] to [1]. If there is a valid message length, the
data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
status to register contents, user selected by writing to the
STATR bits OD4, OD3, OD2, OD1, and OD0. The value of
the previous bits SOA4 and SOA3 will determine which
output the SO information applies to for the registers which
are output specific; viz., Fault, PWMR, CONFR0, CONFR1
and OCR registers.
information for each output (depending on the previous
SOA4, SOA3 state) that was selected during the most recent
STATR write until changed with an updated STATR write.
the STATR-selected register data at the time that the
pulled to a logic [0] during SPI communication, and/or for the
period of time since the last valid SPI communication, with
the following exception:
SERIAL OUTPUT BIT ASSIGNMENT
serial input message, as explained in the following
CS
The GCR register disables the over-voltage protection
The CALR register allows the MCU to calibrate internal
When the
Any bits clocked out of the Serial Output (SO) pin after the
A valid message length is determined following a
SO data will represent information ranging from fault
Note that the SO data will continue to reflect the
The output status register correctly reflects the status of
• The previous SPI communication was determined to be
• The VPWR voltage is below 4.0 V, the status must be
The 16 bits of serial output data depend on the previous
transition, is dependent upon the previously written SPI
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
ignored by the MCU.
CS
pin is pulled low, the output register is
Figure
Analog Integrated Circuit Device Data
12.
CS
Freescale Semiconductor
pin first transitioned to a
CS
CS
is