IR3504MTRPBF International Rectifier, IR3504MTRPBF Datasheet
IR3504MTRPBF
Specifications of IR3504MTRPBF
Related parts for IR3504MTRPBF
IR3504MTRPBF Summary of contents
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... Simplified Power Good (PG) Output provides indication of proper operation and avoids false triggering • Small thermally enhanced 32L MLPQ (5mm x 5mm) package • Over voltage signal to system with over voltage detection during powerup and normal operation • ORDERING INFORMATION Device IR3504MTRPBF * IR3504MPBF * Samples only Page 1 TM XPHASE3 AMD SVID CONTROL IC TM ...
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APPLICATION CIRCUIT 12V RVCCLDRV Power Good SVC SVD PWROK ENABLE CSS/DEL2 CVDAC2 RVDAC2 ROCSET2 RCP2 CCP21 CCP22 PIN DESCRIPTION PIN# PIN SYMBOL 1 SVD SVD (Serial VID Data bidirectional signal that is an input and open drain output ...
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PIN# PIN SYMBOL 8 EAOUT2 Output of the output 2 error amplifier. 9 FB2 Inverting input to the Output 2 error amplifier. 10 VOUT2 Output 2 remote sense amplifier output. 11 VOSEN2+ Output 2 remote sense amplifier input. Connect to ...
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ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltages are absolute voltages referenced to the LGND pin. Operating Junction Temperature……………..0 to 150 Storage Temperature Range………………….-65 ESD Rating………………………………………HBM Class 1C JEDEC ...
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RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN-x ≤ 0.3V, 0 ELECTRICAL CHARACTERISTICS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions (unless otherwise specified). Typical values ...
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PARAMETER OC Delay Time V(IINx) – V(OCSETx) = 500 mV SS/DELx to FBx Input Offset With FBx = 0V, adjust V(SS/DELx) until Voltage EAOUTx drives high Charge Current OC Delay/VID Off Discharge Note 1 Currents Fault Discharge Current Hiccup Duty ...
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PARAMETER Output Voltage Leakage Current VCCL Activation Threshold Over Voltage Protection (OVP) Comparators Threshold at Power-up Voutx Threshold Voltage OVP Release Voltage during Normal Operation Threshold during Dynamic VID down Dynamic VID Detect Comparator Threshold Note 1 Propagation Delay to ...
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PHSOUT FREQUENCY VS RROSC CHART 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 Figure 2 - Phout Frequency vs. RROSC chart Page 8 PHSOUT FREQUENCY vs. RROSC ...
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SYSTEM SET POINT TEST Converter output voltage is determined by the system set point voltage which is the voltage that appears at the FBx pins when the converter is in regulation. The set point voltage includes error terms for the ...
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SYSTEM THEORY OF OPERATION PWM Control Method The PWM block diagram of the xPHASE3 with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. Input voltage ...
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Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) Phase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 ...
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PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE DUTY CYCLE INCREASE OPERATION DUE TO LOAD INCREASE TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response ...
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Figure 7 Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled ...
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IR3504 THEORY OF OPERATION Block Diagram The Block diagram of the IR3504 is shown in Figure 8. The following discussions are applicable to either output plane unless otherwise specified. Serial VID Control The two Serial VID Interface (SVID) pins SVC ...
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VCCLDRV VCCL REGULATOR AMPLIFIER VCCLFB + - 1.2V 0.94 0.86 + VCCL UVLO OV FAULT LATCH - VCCL UVL OV1-2 COMPARATOR S Q SET DISABLE VCCL UVLO DOMINANT OC2 AFTER PG R OC2 CLEARED FAULT LATCH2 OPEN ...
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Table 1 – 2-bit Boot VID codes SVC SVD Output Voltage( Table 3 - AMD 7 BIT SVID CODES SVID [6:0] Voltage (V) SVID [6:0] 000_0000 1.5500 010_0000 000_0001 1.5375 010_0001 000_0010 ...
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Control IC VDAC1 VDAC1 Error Amplifier + EAOUT1 - FB1 IFB VDRP Amplifier VDRP1 - IIN1 + VOUT1 Remote Sense VOSEN1+ + Amplifier VOSEN1- - Figure 9 Adaptive voltage positioning Control IC IFB Remote Sense Amplifier Figure 10 Temperature compensation ...
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Output 1 (VDD) Adaptive Voltage Positioning (continued) The voltage difference between VDRP1 and FB1 represents the gained up average current information. Placing a resistor R between VDRP1 and FB1 converts the gained up current information (in the form of a ...
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VCC (12V) ENABLE 2-Bit Boot VID 2-Bit Boot SVC READ & STORE VID On-Hold 2-Bit Boot VID 2-Bit Boot SVD READ & STORE VID On-Hold 2-Bit Boot VID Voltage 0.8V VDACx 4.0V 3.92V 1.4V SS/DEL EAOUT VOUT PG PWROK START ...
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Serial VID Interface Protocol and VID-on-the-fly Transition The IR3504 supports the AMD SVI bus protocol and the AMD Server and desktop SVI wire protocol which is based 2 on fast-mode I C. SVID commands from an AMD processor are communicated ...
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Over-Current Hiccup Protection after Soft Start The over current limit threshold is set by a resistor connected between OCSET the hiccup over-current protection with delay after PG is asserted. The delay is required since over-current conditions can occur as part ...
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Figure 14 VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz VCCL Under Voltage Lockout (UVLO) The IR3504 does not directly monitor VCC for under voltage lockout but instead monitors the system VCCL supply voltage since this voltage ...
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Open Control Loop Detection The output voltage range of error amplifier is continuously monitored to ensure the voltage loop is in regulation. If any fault condition forces the error amplifier output above VCCL-1.08V for 8 PHSOUT switching cycles, the fault ...
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OUTPUT OVP VOLTAGE THRESHOLD (Vout) VCCL-800 mV IIN (PHASE IC ISHARE) GATEH (PHASE IC) GATEL (PHASE IC) FAULT LATCH ERROR AMPLIFIER VDAC OUTPUT (EAOUT) NORMAL OPERATION Figure 15 - Over-voltage protection during normal operation VID VDAC OV THRESHOLD OUTPUT VOLTAGE ...
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Open Remote Sense Line Protection If either remote sense line VOSEN The IR3504 continuously monitors the VOUT are applied to the VOSEN + and VOSEN X higher than 90% of V(VCCL) will be present at VOSEN be high. If VOSEN ...
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The Fault Table below describes ten different faults that can occur during normal operation and how the IR3504 IC will react to protect the supply and the load from possible damage. The fault types that can occur are listed in ...
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APPLICATIONS INFORMATION Q1 12V CVCCL RVCCLFB1 RVCCLFB2 RVCCLDRV ISHARE2 VDAC2 VDDPWRGD SVC SVD 1 24 SVD LGND ROSC PWROK 2 23 PWROK ROSC RDRP11 U1 ENABLE 3 22 CDRP1 RDRP12 ENABLE VDRP1 IR3504 4 21 IIN2 IIN1 CSS/DEL2 CONTROL CSS/DEL1 ...
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DESIGN PROCEDURES - IR3504 AND IR3505 CHIPSET IR3504 EXTERNAL COMPONENTS All the output components are selected using one output but suitable for both unless otherwise specified. Oscillator Resistor R osc R The IR3504 generates square-wave pulses to synchronize the phase ...
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VDAC Slew Rate Programming Capacitor C The slew rate of VDAC down-slope SR (5), where I is the sink current of VDAC pin. The slew rate of VDAC up-slope is three times greater that of SINK down-slope. The resistor R ...
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No Load Offset Setting Resistor RFB11, RFB13, RTHERM1 and Adaptive Voltage Positioning Resistor RDRP11 for Output1 Define R as the effective offset resistor at room temperature equals to R FB_R offset voltage V (offset above the DAC voltage) and calculating ...
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IR3505 EXTERNAL COMPONENTS Inductor Current Sensing Capacitor C The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor parallel with the inductor are chosen to match the time constant of the ...
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VOLTAGE LOOP COMPENSATION The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop introduces extra zero ...
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Type III Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin ...
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π 2 ∗ f ∗ π 2 ∗ f ∗ CURRENT SHARE LOOP COMPENSATION The internal compensation of current share loop ensures that crossover frequency of the ...
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DESIGN EXAMPLE – AMD FIVE + ONE PHASE DUAL OUTPUT CONVERTER (FIGURE 17) SPECIFICATIONS Input Voltage DAC Voltage: V =1.2 V DAC No Load Output Voltage Offset for output1: V Output1 Current: I =95 ADC O1 ...
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VDAC Slew Rate Programming Capacitor C − ∗ 10 SINK VDAC DOWN − ∗ ...
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R ∗ 577 ROOM DRP n ∗ the case of thermal compensation is required, use equation (14) to (17) to select the R IR3505 ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. Dedicate at least one middle layer for a ground plane LGND. • Connect ...
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PCB METAL AND COMPONENT PLACEMENT • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to prevent shorting. • Lead land length should be equal to maximum part ...
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SOLDER RESIST • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...
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STENCIL DESIGN • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 32L MLPQ ( Body) θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Page 42 o =24.4 C/W, θ JA Data and specifications subject to change without notice. This ...