IR3504MTRPBF International Rectifier, IR3504MTRPBF Datasheet - Page 22

• Manufacturer Part Number: IR3504MTRPBF
• Description: IC CTRL XPHASE3 SVID 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3504MTRPBF

• Applications: Processor
• Current - Supply: 10mA
• Voltage - Supply: 4.75 V ~ 7.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: *
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VCCL Under Voltage Lockout (UVLO)
The IR3504 does not directly monitor VCC for under voltage lockout but instead monitors the system VCCL supply
voltage since this voltage is used for the gate drive. As VCC begins to rise during power up, the VCCLDRV pin will
be high impedance therefore allowing VCCL to roughly follow VCC-NPN
set by resistor divider at VCCLFB pin. At this point, the OV
VCCL voltage drops below 86% of the set value, the SS/DEL CLEARED fault latch will be set.
VID OFF Codes
SVID OFF codes of 111_1100, 111_1101, 111_1110, and 111_1111 turn off the converter by pulling down EAOUT
voltage and discharging SS/DEL
non-off SVID code the converter will turn on and transition to the voltage represented by the SVID as shown in
Figure 10.
Voltage Regulator Ready (PG)
The PG pin is an open-collector output and should have an external pull-up resistor. During soft start, PG remains
low until the output voltage is in regulation and SS/DEL
VCCL is below 86% of target, an over current condition occurs for at least 1024 PHSOUT clocks prior to PG, an
over current condition occurs after PG and SS/DEL
chain condition occurs, VOSNS lines are detected open, VOUT
sensed as operating open loop for 8 PHSOUT cycles. A high level at the PG pin indicates that the converter is in
operation with no fault and ensures the output voltage is within the regulation.
PG monitors the output voltage. If any of the voltage planes fall out of regulation, PG will become low, but the VR
continues to regulate its output voltages. The PWROK input may or may not de-assert prior to the voltage planes
falling out of specification. Output voltage out of spec is defined as 315mV to 275mV below nominal voltage. VID
on-the-fly transition which is a voltage plane transitioning between one voltage associated with one VID code and a
voltage associated with another VID code is not considered to be out of specification.
A PWROK de-assert while ENABLE is high results in all planes regulating to the previously stored 2-bit Boot VID. If
the 2-bit Boot VID is higher than the VID prior to PWROK de-assertion, this transition will NOT be treated as VID on-
the-fly and if either of the two outputs is out of spec high, PG will be pulled down.
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Figure 14 VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz
X
through the 50uA discharge current, but do not drive PG low. Upon receipt of a
X
discharges to the delay threshold, an open phase timing daisy
X
is above 3.9V. The PG pin becomes low if ENABLE is low,
X
and UV CLEARED fault latches will be released. If
X
is 315mV below VDAC
VBE
until VCCL is above 94% of the voltage
X
, or if the error amp is
July 28, 2009
IR3504
X