IR3504MTRPBF International Rectifier, IR3504MTRPBF Datasheet - Page 3

• Manufacturer Part Number: IR3504MTRPBF
• Description: IC CTRL XPHASE3 SVID 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3504MTRPBF

• Applications: Processor
• Current - Supply: 10mA
• Voltage - Supply: 4.75 V ~ 7.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: *
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
8
9
Page 3
PIN SYMBOL
ROSC/OVP
VCCLDRV
VOSEN2+
VOSEN1+
VOSEN2-
VOSEN1-
SS/DEL1
CLKOUT
PHSOUT
EAOUT2
EAOUT1
OCSET1
VCCLFB
VOUT2
VOUT1
VDAC1
VDRP1
PHSIN
LGND
VCCL
SVC
FB2
FB1
IIN1
PG
Output of the output 2 error amplifier.
Inverting input to the Output 2 error amplifier.
Output 2 remote sense amplifier output.
Output 2 remote sense amplifier input. Connect to output at the load.
Output 2 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to output at the load.
Output 1 remote sense amplifier output.
Inverting input to the output 1 error amplifier. Converter output voltage can be
increased from the VDAC1 voltage with an external resistor connected between
VOUT1 and this pin (there is an internal current sink at this pin).
Output of the output 1 error amplifier.
Programs the output 1 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC1 and an internal current
source from this pin. Over-current protection can be disabled by connecting a
resistor from this pin to VDAC1 to program the threshold higher than the possible
signal into the IIN1 pin from the phase ICs but no greater than 5V (do not float this
pin as improper operation will occur).
Output 1 reference voltage programmed by the SVID inputs and error amplifier non-
inverting input. Connect an external RC network to LGND to program dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
Programs output 1 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
Output 1 average current input from the output 1 phase IC(s). This pin is also used
to communicate over voltage condition to phase ICs.
Output 1 Buffered IIN1 signal. Connect an external RC network to FB1 to program
converter output impedance.
Connect a resistor to LGND to program oscillator frequency and OCSET1, OCSET2,
FB1, FB2, VDAC1, and VDAC2 bias currents. Oscillator frequency equals switching
frequency per phase. The pin voltage is 0.6V during normal operation and higher
than 1.6V if over-voltage condition is detected.
Local Ground for internal circuitry and IC substrate connection.
Clock output at switching frequency multiplied by phase number. Connect to CLKIN
pins of phase ICs.
Phase clock output at switching frequency per phase. Connect to PHSIN pin of the
first phase IC.
Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
Output of the voltage regulator, and power input for clock oscillator circuitry. Connect
a decoupling capacitor to LGND.
Non-inverting input of the voltage regulator error amplifier. Output voltage of the
regulator is programmed by the resistor divider connected to VCCL.
Output of the VCCL regulator error amplifier to control external transistor. The pin
senses 12V power supply through a resistor.
Power good signal implemented with an open collector output that drives low during
startup and under any external fault condition. Also, if any of the voltage planes fall
out of spec, it will drive low. Connect external pull-up. (Output voltage out of spec is
defined as 350mV to 240mV below VDAC voltages)
SVC (Serial VID Clock) is an open drain output of the processor and input to
IR3504, requires an external bias voltage and should not be floated
PIN DESCRIPTION
July 28, 2009
IR3504