IR3523MTRPBF International Rectifier, IR3523MTRPBF Datasheet
IR3523MTRPBF
Specifications of IR3523MTRPBF
Related parts for IR3523MTRPBF
IR3523MTRPBF Summary of contents
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... Daisy-chain digital phase timing provides accurate phase interleaving without external components Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO • Over voltage signal to system with over voltage detection during powerup and normal operation • ORDERING INFORMATION Device IR3523MTRPBF * IR3523MPBF * Samples only Page XPHASE3 DUAL OUTPUT CONTROL IC ...
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APPLICATION CIRCUIT 12V PG2 VID2_0 VID2_1 VID2_2 VID1_4 VID1_3 VID1_2 ENABLE 2 ENABLE 1 CSS/DEL2 CVDAC1 ROCSET2 RCP2 CCP22 To Output 2 VOUT2 SENSE + Remote VOUT2 SENSE - Sense PIN DESCRIPTION PIN# PIN SYMBOL 1-3 VID1_4, VID inputs for ...
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PIN# PIN SYMBOL 12 FB2 Output 2 Error Amplifier inverting input 13 VOUT2 Output 2 remote sense amplifier output. 14 VOSEN2+ Output 2 remote sense amplifier input. Connect to output at the load. 15 VOSEN2- Output 2 remote sense amplifier ...
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ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltages are absolute voltages referenced to the LGND pin. Operating Junction Temperature……………..0 to 150 Storage Temperature Range………………….-65 ESD Rating………………………………………HBM Class 1C JEDEC ...
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RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN-x ≤ 0.3V, 0 ELECTRICAL CHARACTERISTICS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions (unless otherwise specified). Typical values ...
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PARAMETER Soft Start and Delay Start Delay Measure Enable to EAOUTx activation Start-up Time Measure Enable activation to PGx OC Delay Time V(IINx) – V(OCSETx) = 500 mV SS/DELx to FB Input Offset With FB = 0V, adjust V(SS/DEL) until ...
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PARAMETER Over Voltage Protection (OVP) Comparators Threshold at Power-up (Output 2) Threshold at Power-up (Output 1) Voutx Threshold Voltage Compare to V(VDACx) OVP Release Voltage during Compare to V(VDACx) Normal Operation Threshold during Dynamic VID down (Output 2) Threshold during ...
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PHSOUT FREQUENCY VS RROSC CHART PHSOUT FREQUENCY vs. RROSC 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 Figure 2 - PHSout Frequency vs. RROSC chart Page ...
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IR3523 block diagram ENABLE2 250nS - BLANKING + ENABLE 1.65V 1.0V COMPARATOR PG2 UV2 SSCLF2 DLY OUT2 400k VCCLDRV OV1_2 VCCL REGULATOR AMPLIFIER VCCLFB + - 0.94 1.2V 0. VCCL UVL UV CLEARED COMPARATOR FAULT LATCH2 OV OPEN ...
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SYSTEM SET POINT TEST Converter output voltage is determined by the system set point voltage which is the voltage that appears at the FBx pins when the converter is in regulation. The set point voltage includes error terms for the ...
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SYSTEM THEORY OF OPERATION PWM Control Method The PWM block diagram of the xPHASE3 with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. Input voltage ...
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Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) Phase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 ...
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PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE DUTY CYCLE INCREASE OPERATION DUE TO LOAD INCREASE TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response ...
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Figure 8 - Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or ...
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IR3523 THEORY OF OPERATION Block Diagram The Block diagram of the IR3523 is shown in Figure 3, and specific features are discussed in the following sections. All the features are described using one output but suitable for both unless otherwise ...
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Output 1 (Vtt) Adaptive Voltage Positioning Adaptive Voltage Positioning is needed to reduce the output voltage deviations during load transients and the power dissipation of the load at heavy load. IR3523 only provides AVP on output1. The circuitry related to ...
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Output1 Inductor DCR Temperature Compensation A negative temperature coefficient (NTC) thermistor can be used for Output1 inductor DCR temperature compensation. The thermistor should be placed close to the Output1 inductors and connected in parallel with the feedback resistor, as shown ...
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Figure 11 depicts the start-up sequence. If the ENABLE input is asserted and there are no faults, the SS/DELx pins will start charging, the VID codes are read and stored. VDAC2 transitions to the stored VID code, while VDAC1 transitions ...
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Over-Current Hiccup Protection after Soft Start The over current limit threshold is set by a resistor connected between OCSETx and VDACx pins. Figure 12 shows the hiccup over-current protection with delay after PGx is asserted. The delay is required since ...
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Figure 13 - VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz VCCL Under Voltage Lockout (UVLO) The IR3523 has no under voltage lockout protection for the converter input voltage (VCC), but monitors the VCCL voltage instead. The ...
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Enable Input Pulling the ENABLE pin below 1.0 V sets the Fault Latch. Forcing ENABLE to a voltage above 1.65V results in the 3-bit VID codes to be read and stored. SS/DEL fault conditions are present. Over Voltage Protection (OVP) ...
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VID VDAC OV THRESHOLD OUTPUT VOLTAGE VDAC (VO) NORMAL OPERATION Figure 15 - Over-voltage protection during dynamic VID Open Remote Sense Line Protection If either remote sense line VOSEN The IR3523 continuously monitors the VOUT are applied to the VOSEN ...
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The Fault Table below describes ten different faults that can occur during normal operation and how the IR3523 IC will react to protect the supply and the load from possible damage. The fault types that can occur are listed in ...
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APPLICATIONS INFORMATION P12V_DDR3_FILTED Q16 R55 C131 R54 R56 R65 VDDR3_VRRDY VID_DDR3_0 VID_DDR3_1 VID_DDR3_2 U1 VID_VTT_4 1 VID_VTT_3 VID1_4 NC3 VID_VTT_2 2 VID1_3 LGND 3 VID1_2 PG1 4 ENABLE_DDR3 ENABLE2 ROSC/OVP IR3523 5 ENABLE_VTT ENABLE1 VDRP1 CONTROL 6 IIN2 IIN1 IC ...
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DESIGN PROCEDURES - IR3523 AND IR3505 CHIPSET IR3523 EXTERNAL COMPONENTS All the output components are selected using one output but suitable for both unless otherwise specified. Oscillator Resistor Rosc The IR3523 generates square-wave pulses to synchronize the phase ICs. The ...
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VDAC Slew Rate Programming Capacitor C The slew rate of VDACx down-slope SR (5), where I is the sink current of VDAC pin. The slew rate of VDAC up-slope is three times greater that of SINK down-slope. The resistor R ...
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No Load Offset Setting Resistor RFB11, RFB13, RTHERM1 and Adaptive Voltage Positioning Resistor RDRP11 for Output1 Define R is the effective offset resistor at room temperature equals to R FB_R offset voltage V above the DAC voltage, calculate the sink ...
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VOLTAGE LOOP COMPENSATION The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop introduces extra zero ...
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Type III Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin ...
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π 2 ∗ f ∗ π 2 ∗ f ∗ CURRENT SHARE LOOP COMPENSATION The internal compensation of current share loop ensures that crossover frequency of the ...
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Soft Start Capacitor C SS/DEL Determine the soft start capacitor from the required soft start time. − CHG DEL Vboot − ...
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The over current set resistor (Rocset) can be calculated as follows: I LIMIT ∗ R ∗ OCSET − ∗ ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. Dedicate at least one middle layer for a ground plane LGND. • Connect ...
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PCB METAL AND COMPONENT PLACEMENT • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...
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SOLDER RESIST • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...
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STENCIL DESIGN • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 40L MLPQ ( BODY) Θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Page C/W, Θ Data and specifications ...