MAX16066ETL+ Maxim Integrated Products, MAX16066ETL+ Datasheet - Page 25

• Manufacturer Part Number: MAX16066ETL+
• Description: IC SYSTEM MANAGER 8CH 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX16066ETL+

• Applications: Power Supply Monitor, Sequencer
• Voltage - Supply: 2.8 V ~ 14 V
• Current - Supply: 4.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Number Of Voltages Monitored: 8
• Undervoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Yes
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 200 us
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10 mA
• Maximum Power Dissipation: 2105 mW
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Chip Enable Signals: No
• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table
GPIO1 to GPIO8 are configurable to assert low when
the voltage across CSP and CSM exceed the primary
overcurrent threshold. See the Internal Current-Sense
Amplifier section for more details.
GPIO3 and GPIO8 are configurable to indicate a fault
during power-up or power-down on the secondary
sequence. This output asserts low when a MON_ input
exceeds the overvoltage or undervoltage threshold. The
sequencer will still enter the fault state and turn off all the
EN_OUT_ outputs assigned to the secondary sequence.
GPIO1, GPIO3, GPIO5, and GPIO7 are configurable to
act as an active-low manual reset input, MR. Drive MR
low to assert RESET. RESET remains asserted for the
selected reset timeout period after MR transitions from
low to high. See the RESET2 Output section for more
information on selecting a reset timeout period.
GPIO2, GPIO6, and GPIO8 are configurable to act as
a reset indicator related to the secondary sequence.
RESET2 asserts during power-up/power-down and deas-
serts following the reset timeout period once the power-
up of the secondary sequence is complete. The second-
ary power-up sequence is completed when any MON_
inputs assigned to Slot 12 exceed the undervoltage
thresholds and Slot 12 sequence delay expires. When
12-Channel/8-Channel, Flash-Configurable System
REGISTER
ADDRESS
39h
3Ah
14. Fault1 and Fault2 Dependencies (continued)
Managers with Nonvolatile Fault Registers
______________________________________________________________________________________
ADDRESS
Overcurrent Comparator (OVERC)
FLASH
23Ah
239h
Fault-On Power-Up (FAULTPU)
RANGE
Manual Reset (MR)
RESET2 Output
[7:2]
BIT
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
1 = Fault2 depends on MON9
1 = Fault2 depends on MON10
1 = Fault2 depends on MON11
1 = Fault2 depends on MON12
1 = Fault2 depends on the overvoltage thresholds of the inputs selected by
r38h and r39h[3:0]
1 = Fault2 depends on the undervoltage thresholds of the inputs selected
by r38h and r39h[3:0]
1 = Fault2 depends on the early warning thresholds of the inputs selected
by r38h and r39h[3:0]
0 = Fault2 is an active-low digital output
1 = Fault2 is an active-high digital output
1 = Fault1 depends on secondary overcurrent comparator
1 = Fault2 depends on secondary overcurrent comparator
Reserved
no MON_ inputs are assigned to Slot 12, the power-up
sequence is complete after the slot sequence delay
expires. RESET2 shares configuration bits with RESET
with the exception of polarity (active-high or active-low)
and output type (push-pull or open drain), see Table 23.
During normal monitoring, RESET2 can be configured
to assert when any combination of MON_ inputs violates
configurable combinations of thresholds: undervoltage,
overvoltage, or early warning. Select the combination of
thresholds using r3Bh[1:0], and select the combination
of MON_ inputs using r3Ch[7:1] and r3Dh[4:0]. Note that
MON_ inputs in the secondary sequence configured as
critical faults will always cause RESET2 to assert regard-
less of these configuration bits.
RESET2 can be configured as push-pull or open drain
using the appropriate GPIO_ configuration bit in r42h
(see Table 12), and is always active-low. Select the
reset timeout for RESET and RESET2 by loading a value
from Table 5 into r3Bh[7:4]. RESET and RESET2 can be
forced to assert by writing a ‘1’ into r3Ch[0]. RESET2
remains asserted for the reset timeout period after a ‘0’
is written into r3Ch[0].
GPIO2, GPIO4, GPIO6, and GPIO8 are configurable as
the watchdog timer output, WDO. GPIO1 is configurable
as WDI. See Table 24 for configuration details. WDO is an
active-low output. See the Watchdog Timer section for more
information about the operation of the watchdog timer.
Watchdog Input (WDI) and Output (WDO)
DESCRIPTION
25