ISL8724IRZ Intersil, ISL8724IRZ Datasheet

IC POWER SUPPLY SEQUENCER 24QFN

ISL8724IRZ

Manufacturer Part Number
ISL8724IRZ
Description
IC POWER SUPPLY SEQUENCER 24QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL8724IRZ

Applications
Power Supply Sequencer
Voltage - Supply
2.5 V ~ 5 V
Current - Supply
270µA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Input
-
Power Sequencing Controllers
The Intersil ISL8723 and ISL8724 are 4 channel sequencers
controlling the on and off sequence of voltages with
undervoltage supply fault protection and a “sequence
completed” signal (RESET). For larger systems, more than 4
voltages can be sequenced by a simple connection of
multiple IC's. These sequencers use an integrated charge
pump to drive 4 external low-cost N-channel MOSFET
switch gates above the IC bias voltage by 5.3V. These IC's
can be biased from and control any supply from 2.5V to 5V
and additionally monitor any voltage above 0.7V. Individual
product descriptions follow.
The four channel ISL8723 (ENABLE input), ISL8724
(ENABLE input) offer the designer 4 voltage control when it
is required that all four rails are in minimal compliance prior
to turn on and that compliance must be maintained during
operation. The ISL8723 has a low power standby mode
when it is disabled suitable for battery powered applications.
External resistors provide flexible voltage threshold
programming of monitored voltages. Delay and sequencing
timing are programmable by external capacitors for both
ramp up and ramp down.
Ordering Information
ISL8723IRZ*
ISL8724IRZ*
ISL8723EVAL1
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
PART NUMBER
(Note)
87 23IRZ
87 24IRZ
Evaluation Platform
MARKING
PART
®
1
-40 to +85 24 Ld 4x4 QFN L24.4x4
-40 to +85 24 Ld 4x4 QFN L24.4x4
RANGE
TEMP.
(°C)
Data Sheet
PACKAGE
(Pb-free)
1-888-INTERSIL or 1-888-468-3774
DWG. #
PKG.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Enables arbitrary turn-on and turn-off sequencing of up to
• Operates from 2.5V to 5V supply voltage
• Supplies V
• Adjustable voltage slew rate for each rail
• Multiple sequencers can be easily daisy-chained to
• Glitch immunity
• Undervoltage lockout for each monitored supply voltage
• 30µA Sleep State (ISL8723)
• Active high (ISL8723) or low (ISL8724) ENABLE input
• Pb-free (RoHS compliant)
Applications
• Graphics cards
• FPGA/ASIC/microprocessor/PowerPC supply sequencing
• Network Routers
• Telecommunications Systems
Pinout
four power supplies (0.7V to 5V)
sequence an infinite number of independent voltages
DLY_OFF_C
DLY_OFF_D
ENABLE/
ENABLE
GATE_A
GATE_B
GATE_C
All other trademarks mentioned are the property of their respective owners.
April 22, 2009
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
DD
1
2
3
4
5
6
Copyright Intersil Americas Inc. 2006, 2009. All Rights Reserved.
+5.3V of charge pumped gate drive
24
7
ISL8723, ISL8724
23
8
(24 LD QFN)
TOP VIEW
4mmx4mm
ISL8723, ISL8724
22
9
21
10
11
20
12
19
18
17
16
15
14
13
FN6413.1
DLY_OFF_A
UVLO_C
DLY_ON_C
DLY_ON_D
UVLO_D
DLY_OFF_B

Related parts for ISL8724IRZ

ISL8724IRZ Summary of contents

Page 1

... RANGE (Note) MARKING (°C) ISL8723IRZ* 87 23IRZ - 4x4 QFN L24.4x4 ISL8724IRZ* 87 24IRZ - 4x4 QFN L24.4x4 ISL8723EVAL1 Evaluation Platform *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ ...

Page 2

AIN BIN CIN DIN V DD UVLO_A ENABLE UVLO_B SYSRST UVLO_C RESET UVLO_D GROUND FIGURE 1. TYPICAL ISL8723 APPLICATION USAGE Pin Descriptions PIN PIN # NAME FUNCTION 23 VDD Chip Bias 10, 19 GND Bias Return 1 ENABLE/ Input to ...

Page 3

Pin Descriptions (Continued) PIN PIN # NAME FUNCTION 18 DLY_OFF_A Gate Off Delay Timer Output 13 DLY_OFF_B 3 DLY_OFF_C 4 DLY_OFF_D 2 GATE_A FET Gate Drive Output 5 GATE_B 6 GATE_C 7 GATE_D 22 SYSRST System Reset I ...

Page 4

... Ld 4x4 QFN Package . . . . . . . . . . . DD +0.3V DD Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +125°C +0.3V Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C DD Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = T = -40°C to +85°C, Unless Otherwise Specified. Parameters with MIN and/or MAX A J SYMBOL TEST CONDITIONS +25° ...

Page 5

Electrical Specifications V = 3.3V to +5V limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYSRST Low Output Voltage SYSRST Output Capacitance SYSRST Low to ...

Page 6

As an input pulled low all GATEs will be unconditionally shut off and RESET pulled low (see Figure 18). This pin can ...

Page 7

UVLO_X>VUVLOVth ENABLE(ISL8723) ENABLE (ISL8724) DLYOFF_A DLYOFF_B DLYOFF_C DLYOFF_D GATE_C GATE_D GATE_A GATE_B RESET SYSRST FIGURE 4. ISL8723, ISL8724 TURN-OFF TIMING DIAGRAM Typical Performance Curves 0.30 0.25 0. 3.3V 0.15 0.10 0.05 0.00 -40 - ...

Page 8

Typical Performance Curves 1.29 DLY_OFF Vth 1.28 1.27 1.26 DLY_ON Vth 1.25 1.24 1.23 -40 - TEMPERATURE (°C) FIGURE 9. BIAS POWER ON RESET 10.3 10.2 10.1 10.0 9.9 I_GATE_OFF 9.8 9.7 9.6 9.5 9.4 -40 -20 ...

Page 9

Typical Performance Waveforms ENABLE SYSRST I/O = 5V/DIV 5VOUT 3.3VOUT 1.5VOUT VOUT = 2V/DIV FIGURE 13. ISL8723 SEQUENCED TURN-ON EN 5V/DIV t delENLO DLY_ON 0.5V/DIV FIGURE 15. ISL8723 3.3V TURN-ON FIGURE 17. SYSRST AND RESET vs VDD (EN = VDD, ...

Page 10

Typical Performance Waveforms FIGURE 19. 4 UVLOs VALID, ENABLE HIGH TO SYSRST HIGH 10 ISL8723, ISL8724 (Continued) SYSRST SYSRST RESET ENABLE ENABLE FIGURE 20. ENABLE LOW TO RESET AND SYSRST LOW UVLO RESET SYSRST FIGURE 21. UVLO INVALID TO RESET ...

Page 11

7.681k 4.99k 6.98k 8.45k R12 R5 R3 R11 4.99k 1.47k 2.26k 3.01k 1 22 SYSRST 9, ISL8723, ISL8724 + 1µ ...

Page 12

... The sequencing is straight forward across multiple sequencers as all DLY_ON capacitors will simultaneously 12 ISL8723, ISL8724 COMPONENT DESCRIPTION Intersil, ISL8723IR 4 Supply Sequencer FDS6990S or equivalent, Dual N-Channel MOSFET 8.45kΩ 1%, 0402 1.47kΩ 1%, 0402 7.68kΩ 1%, 0402 2.26kΩ 1%, 0402 6.98kΩ ...

Page 13

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

Page 14

Package Outline Drawing L24.4x4 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 4.00 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 14 ISL8723, ...

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