ISL8724IRZ Intersil, ISL8724IRZ Datasheet - Page 2

• Manufacturer Part Number: ISL8724IRZ
• Description: IC POWER SUPPLY SEQUENCER 24QFN
• Manufacturer: Intersil

Specifications of ISL8724IRZ

• Applications: Power Supply Sequencer
• Voltage - Supply: 2.5 V ~ 5 V
• Current - Supply: 270µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

Pin Descriptions
10, 19
DIN
PIN
FIGURE 1. TYPICAL ISL8723 APPLICATION
23
24
20
12
17
14
21
16
15
#
1
8
CIN
DLY_ON_A
DLY_ON_B
DLY_ON_C
DLY_ON_D
V
ENABLE
SYSRST
RESET
GROUND
ENABLE/
DD
ENABLE
UVLO_A
UVLO_B
UVLO_C
UVLO_D
RESET
NAME
GND
VDD
PIN
BIN
USAGE
AIN
Chip Bias
Bias Return
Input to start on/off
sequencing
RESET Output
Undervoltage Lock
Out/Monitoring
Input
Gate On Delay
Timer Output
FUNCTION
UVLO_A
UVLO_B
UVLO_D
UVLO_C
2
AOUT
BOUT
COUT
DOUT
Bias IC from nominal 2.5V to 5V
IC ground.
NOTE: Pin 19 internally tied to GND with 6kΩ. This pin can be tied to GND or left open.
Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is
disabled for 10ms after UVLO is satisfied. ISL8723 has ENABLE. ISL8724 has ENABLE.
RESET provides a high signal ~160ms after all GATEs are fully enhanced. This delay is for stabilization
of output voltages. RESET will assert low upon any UVLO not being satisfied or ENABLE/ENABLE being
deasserted. The RESET output is an open drain N-channel FET and is guaranteed to be in the correct
state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X.
These inputs provide for a programmable UV lockout referenced to an internal 0.631V reference and
are filtered to ignore short (<7µs) transients below programmed UVLO level.
Allows for programming the delay and sequence for V
cap is charged with 1µA, 10ms after turn-on initiated by ENABLE/ENABLE with an internal current
source providing delayed enhancement of the associated FETs GATE to turn-on.
UVLOX
DLY_ONX
ISL8723, ISL8724
0.633V
1.26V
1µA
FILTER
30µs
DLY_OFFX
1.26V
SYSRST
VDD
1µA
FIGURE 2. ISL8723 BLOCK DIAGRAM (1/4)
EN
DESCRIPTION
LOCK OUT
OUT
BIAS
turn-on using a capacitor to ground. Each
LOGIC
RISING DELAY
10ms
10µA
Q-PUMP
VDD+5V
RISING DELAY
150ms
-10µA
April 22, 2009
RESET
FN6413.1
GATEX