STTS424E02BDN3F STMicroelectronics, STTS424E02BDN3F Datasheet - Page 27

• Manufacturer Part Number: STTS424E02BDN3F
• Description: IC TEMP SENSOR 2KB EEPRM 8-TDFN
• Manufacturer: STMicroelectronics

Specifications of STTS424E02BDN3F

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Register Bank
• Sensor Type: Internal
• Sensing Temperature: -40°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Temperature Threshold: + 150 C
• Full Temp Accuracy: +/- 1 C
• Digital Output - Bus Interface: 2-Wire, I2C
• Digital Output - Number Of Bits: 10 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Current: 100 uA
• For Use With: 497-8843 - EVAL DAUGHTER STTS424E02 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8284-2

STTS424E02
5
5.1
5.2
SPD EEPROM operation
2 Kb SPD EEPROM operation
The 2 Kb serial EEPROM is able to lock permanently the data in its first half (from location
00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual inline
memory modules) with serial presence detect. All the information concerning the DRAM
module configuration (such as its access speed, its size, its organization) can be kept write
protected in the first half of the memory.
The first half of the memory area can be write-protected using two different software write
protection mechanisms. By sending the device a specific sequence, the first 128 bytes of
the memory become write protected: permanently or resetable.
These I
organized as 256x8 bits.
I
The device carries a built-in 4-bit device type identifier code (1010) in accordance with the
I
(0110) to define the protection. These codes are used together with the voltage level applied
on the three chip enable inputs (A2, A1, A0). These input signals are used to set the value
that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select
code. In the end application, A0, A1 and A2 must be directly (not through a pull-up or pull-
down resistor) connected to V
inputs are not connected, an internal pull-down circuitry makes (A0,A1,A2) = (0,0,0).
The A0 input is used to detect the V
(refer to
The device behaves as a slave device in the I
synchronized by the serial clock. Read and write operations are initiated by a START
condition, generated by the bus master. The START condition is followed by a device select
code and R/W bit (as described in
acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master,
the bus master acknowledges the receipt of the data byte in the same way. Data transfers
are terminated by a STOP condition after an ACK for WRITE, and after a NoACK for READ.
Internal device reset - SPD EEPROM
In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included.
At power-up (phase during which V
device will not respond to any instruction until V
threshold voltage (this threshold is lower than the minimum V
Table 2: AC SMBus and I
threshold, the device is reset.
2
2
C uses a two wire serial interface, comprising a bi-directional data line and a clock line.
C bus definition to access the memory area and a second device type identifier code
2
Table 20: Device select
C-compatible electrically erasable programmable memory (EEPROM) devices are
2
C compatibility
DD
Doc ID 13448 Rev 8
code).
or V
Table 20: Device select
DD
HV
SS
is lower than V
voltage, when decoding an SWP or CWP instruction
to establish the device select code. When these
timings). Once V
2
C protocol, with all memory operations
DD
has reached the power on reset
DD
min but increases continuously), the
DD
code), terminated by an
DD
has passed the POR
operating voltage defined in
SPD EEPROM operation
th
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bit