STTS424E02BDN3F STMicroelectronics, STTS424E02BDN3F Datasheet - Page 33

• Manufacturer Part Number: STTS424E02BDN3F
• Description: IC TEMP SENSOR 2KB EEPRM 8-TDFN
• Manufacturer: STMicroelectronics

Specifications of STTS424E02BDN3F

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Register Bank
• Sensor Type: Internal
• Sensing Temperature: -40°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Temperature Threshold: + 150 C
• Full Temp Accuracy: +/- 1 C
• Digital Output - Bus Interface: 2-Wire, I2C
• Digital Output - Number Of Bits: 10 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Current: 100 uA
• For Use With: 497-8843 - EVAL DAUGHTER STTS424E02 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8284-2

STTS424E02
5.6
5.6.1
Read operations - SPD
Read operations are performed independently of whether hardware or software protection
has been set.
The device has an internal address counter which is incremented each time a byte is read.
Figure 14. Read mode sequences - SPD
1. The seven most significant bits of the device select code of a random read (in the 1
Random address read - SPD
A dummy write is first performed to load the address into this address counter (as shown in
Figure
condition, and repeats the device select code, with the R/W bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a stop condition.
be identical.
14) but without sending a stop condition. Then, the bus master sends another start
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
DEV SEL
DEV SEL
DEV SEL
DEV SEL
ACK
Doc ID 13448 Rev 8
DATA OUT N
(1)
(1)
R/W
R/W
R/W
R/W
ACK
ACK
ACK
ACK
NO ACK
BYTE ADDR
BYTE ADDR
DATA OUT 1
DATA OUT
NO ACK
ACK
ACK
ACK
DEV SEL
DEV SEL
(1)
(1)
ACK
ACK
ACK
R/W
R/W
SPD EEPROM operation
DATA OUT N
DATA OUT 1
DATA OUT
st
and 3
NO ACK
NO ACK
rd
ACK
bytes) must
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