STTS424E02BDN3F STMicroelectronics, STTS424E02BDN3F Datasheet - Page 28

• Manufacturer Part Number: STTS424E02BDN3F
• Description: IC TEMP SENSOR 2KB EEPRM 8-TDFN
• Manufacturer: STMicroelectronics

Specifications of STTS424E02BDN3F

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Register Bank
• Sensor Type: Internal
• Sensing Temperature: -40°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Temperature Threshold: + 150 C
• Full Temp Accuracy: +/- 1 C
• Digital Output - Bus Interface: 2-Wire, I2C
• Digital Output - Number Of Bits: 10 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Current: 100 uA
• For Use With: 497-8843 - EVAL DAUGHTER STTS424E02 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8284-2

SPD EEPROM operation
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Prior to selecting the memory and issuing instructions, a valid and stable V
be applied. This voltage must remain stable and valid until the end of the transmission of the
instruction and, for a write instruction, until the completion of the internal write cycle (t
At power-down (phase during which V
from the normal operating voltage below the power on reset threshold voltage, the device
stops responding to any instruction sent to it.
Table 20.
1. The most significant bit, b7, is sent first.
2. A0, A1 and A2 are compared against the respective external pins on the memory device.
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in
The device select code consists of a 4-bit device type identifier, and a 3-bit chip enable
“Address” (A2, A1, A0). To address the memory array, the 4-bit device type identifier is
1010b; to access the write-protection settings, it is 0110b.
Up to eight memory devices can be connected on a single I
unique 3-bit code on the chip enable (A0, A1, A2) inputs. When the device select code is
received, the device only responds if the chip enable address is the same as the value on
the chip enable (A0, A1, A2) inputs.
The 8
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on serial data (SDA) during the 9
the device select code, it deselects itself from the bus, and goes into standby mode. The
operating modes are detailed in
Memory area select code
(two arrays)
Set write protection
(SWP)
Clear write protection
(CWP)
Permanently set write
protection (PSWP)
Read SWP
Read CWP
Read PSWP
Table 20: Device select code
th
bit is the Read/Write bit (R/W). This bit is set to 1 for read and 0 for write operations.
(2)
(2)
Device select code
(2)
V
V
V
V
A2
A2
A2
SS
SS
SS
SS
Chip enable
signals
Doc ID 13448 Rev 8
(on serial data (SDA), most significant bit first).
V
V
V
V
Table
A1
A1
A1
DD
DD
SS
SS
V
V
V
V
DD
21.
A0
A0
A0
HV
HV
HV
HV
decreases continuously), as soon as V
b7
Device type identifier
1
0
(1)
th
b6
0
1
bit time. If the device does not match
b5
1
1
2
C bus. Each one is given a
b4
0
0
Chip enable bits
A2
A2
A2
b3
0
0
0
0
DD
A1
A1
A1
b2
0
1
0
1
STTS424E02
voltage must
DD
A0
A0
A0
b1
1
1
1
1
drops
W
R/W
R/W
).
b0
0
0
0
1
1
1