STTS424E02BDN3F STMicroelectronics, STTS424E02BDN3F Datasheet - Page 31

• Manufacturer Part Number: STTS424E02BDN3F
• Description: IC TEMP SENSOR 2KB EEPRM 8-TDFN
• Manufacturer: STMicroelectronics

Specifications of STTS424E02BDN3F

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Register Bank
• Sensor Type: Internal
• Sensing Temperature: -40°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Temperature Threshold: + 150 C
• Full Temp Accuracy: +/- 1 C
• Digital Output - Bus Interface: 2-Wire, I2C
• Digital Output - Number Of Bits: 10 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Current: 100 uA
• For Use With: 497-8843 - EVAL DAUGHTER STTS424E02 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8284-2

STTS424E02
5.5.1
5.5.2
Byte write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is hardware write-protected, the device replies to the data byte with
NoACK, and the location is not modified. If, instead, the addressed location is not write-
protected, the device replies with ACK. The bus master terminates the transfer by
generating a stop condition, as shown in
Page write
The page write mode allows up to 16 bytes to be written in a single write cycle, provided that
they are all located in the same page in the memory: that is, the most significant memory
address bits are the same. If more bytes are sent than will fit up to the end of the page, a
condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become
overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device. After each byte is transferred, the internal byte address counter (the 4 least
significant address bits only) is incremented. The transfer is terminated by the bus master
generating a stop condition.
Figure 12. Write mode sequences in a non write-protected area of SPD
BYTE WRITE
PAGE WRITE
Doc ID 13448 Rev 8
DEV SEL
DEV SEL
ACK
DATA IN N
Figure
R/W
R/W
ACK
ACK
BYTE ADDR
BYTE ADDR
ACK
12.
ACK
ACK
DATA IN 1
DATA IN
SPD EEPROM operation
ACK
ACK
DATA IN 2
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