ADM1033ARQZ-REEL7 ON Semiconductor, ADM1033ARQZ-REEL7 Datasheet - Page 12

• Manufacturer Part Number: ADM1033ARQZ-REEL7
• Description: IC THERM/FAN SPEED CTRLR 16-QSOP
• Manufacturer: ON Semiconductor

Specifications of ADM1033ARQZ-REEL7

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Block Write
to a slave address as follows. A maximum of 32 bytes can be
written.
Read Operations
Receive Byte
The register address must be set up prior to this, with the
MSB at 0 to read a single byte. In this operation, the master
device receives a single byte from a slave device as follows:
a single byte from a register whose address has previously
been set by a send byte or write byte operation.
Block Read
slave device. The number of bytes to be read must be set in
advance. To do this, use a write byte operation to the
#Bytes/Block Read Register at Address 0x00. The register
address determines whether a block−read or a read−byte
operation is to be completed (set MSB to 1 to specify a
block−read operation). A maximum of 32 bytes can be read.
In this operation, the master device writes a block of data
This is useful when repeatedly reading a single register.
In the ADM1033, the receive byte protocol is used to read
In this operation, the master reads a block of data from a
S
10. The master asserts a stop condition on SDA to end
ADDRESS
1. The master asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address. The register
5. The slave asserts ACK on SDA.
6. The master sends the byte count.
7. The slave asserts ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts ACK on SDA after each byte.
1. The master device asserts a start condition on
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master sends NO ACK on SDA.
6. The master asserts a stop condition on SDA, and
1. The master asserts a start condition on SDA.
SLAVE
by a write bit (low).
address sets up the address pointer register and
determines whether a block write (MSB = 1) or a
byte write (MSB = 0) takes place.
the transaction.
SDA.
by the read bit (high).
the transaction ends.
W A
Figure 22. Block Write to RAM
S
REGISTER
ADDRESS
Figure 23. Receive Byte
ADDRESS
SLAVE
A
COUNT
BYTE
R A
A
DATA
DATA 1
A P
A
DATA 2
A
DATA N
http://onsemi.com
A P
12
SMBus Timeout
feature. When this is enabled, the SMBus typically times out
after 25 ms of no activity. The timeout is disabled by default.
It prevents hangups by releasing the bus after a period of
inactivity.
(Bit 5) of Configuration Register 1 (Address 0x01) to 1.
of Configuration Register 1 (Address 0x01) to 1.
Packet Error Checking (PEC)
(PEC). This optional feature is triggered by the extra clock
for the PEC byte. The PEC byte is calculated using CRC−8.
The frame check sequence (FCS) conforms to CRC−8 by the
following:
For more information, consult www.SMBus.org.
Alert Response Address (ARA)
feature allows an interrupting device to identify itself to the
host.
as an SMBusALERT. One or more ALERT outputs can be
connected to a common SMBusALERT line, connected to
the master.
S
The ADM1033 has a programmable SMBus timeout
To enable the SDA timeout, set the SDA timeout bit
To enable the SCL timeout, set the SCL timeout bit (Bit 4)
The ADM1033 also supports packet error checking
When multiple devices exist on the same bus, the ARA
The ALERT output can be used as an interrupt output or
10. The master asserts ACK on SDA.
12. The master asserts ACK on SDA after each data
13. The master does not acknowledge after the Nth
14. The master asserts a stop condition on SDA to end
11. The slave sends N data bytes.
ADDRESS
SLAVE
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address (MSB = 1).
5. The slave asserts ACK on SDA.
6. The master asserts a repeated start on SDA.
7. The master sends the 7−bit slave address followed
8. The slave asserts ACK on SDA.
9. The slave sends the byte count.
by the write bit (low).
by the read bit (high).
byte.
data byte.
the transaction.
Figure 25. ALERT Response Address
W A
Figure 24. Block Read from RAM
S
C(x) + x
ALERT RESPONSE
REGISTER
ADDRESS
ADDRESS
8
A
) x
S
ADDRESS
SLAVE
2
) x ) 1
R A
R A
ADDRESS
DEVICE
COUNT
BYTE
A
DATA 1
A P
A DATA N
(eq. 1)
A
P