ISL6268CAZ Intersil, ISL6268CAZ Datasheet - Page 13

IC PWM CTRLR SYNC BUCK 16-QSOP

ISL6268CAZ

Manufacturer Part Number
ISL6268CAZ
Description
IC PWM CTRLR SYNC BUCK 16-QSOP
Manufacturer
Intersil
Datasheet

Specifications of ISL6268CAZ

Pwm Type
Controller
Number Of Outputs
1
Frequency - Max
600kHz
Voltage - Supply
7 V ~ 25 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-10°C ~ 100°C
Package / Case
16-QSOP
Frequency-max
600kHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Duty Cycle
-

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EN (Pin 5), and PGOOD (Pin 2)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
COMP (Pin 6), FB (Pin 7), and VO (Pin 10)
For best results, use an isolated sense line from the output
load to the VO pin. The input impedance of the FB pin is
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND
pins keeping the high impedance trace short.
FSET (Pin 9)
This pin requires a quiet environment. The resistor R
and capacitor C
this pin. Keep fast moving nodes away from this pin.
ISEN (Pin 11)
Route the connection to the ISEN pin away from the traces
and components connected to the FB pin, COMP pin, and
FSET pin.
FSET
should be placed directly adjacent to
13
FSET
ISL6268
LG (Pin 13)
The signal going through this trace is both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the PGND pin.
These two traces should be short, wide, and away from
other traces. There should be no other weak signal traces in
proximity with these traces on any layer.
BOOT (Pin 15), UG (Pin 16), and PHASE (Pin 1)
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UG and PHASE pins in parallel with short
and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
August 22, 2006
FN6348.0

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