ISL6268CAZ Intersil, ISL6268CAZ Datasheet - Page 8

• Manufacturer Part Number: ISL6268CAZ
• Description: IC PWM CTRLR SYNC BUCK 16-QSOP
• Manufacturer: Intersil

Specifications of ISL6268CAZ

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 600kHz
• Voltage - Supply: 7 V ~ 25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -10°C ~ 100°C
• Package / Case: 16-QSOP
• Frequency-max: 600kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -

The ISL6268 has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The LG gate-driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant, requiring a low
r
order to clamp the gate of the MOSFET below the V
turn-off. The current transient through the gate at turnoff can
be considerable because the switching charge of a low
r
protection prevents a gate-driver output from turning on until
the opposite gate-driver output has fallen below
approximately 1V. The dead-time shown in Figure 4 is
extended by the additional period that the falling gate voltage
stays above the 1V threshold. The high-side gate-driver
output voltage is measured across the UG and PHASE pins
while the low-side gate-driver output voltage is measured
across the LG and PGND pins. The power for the LG
gate-driver is sourced directly from the PVCC pin. The power
for the UG gate-driver is sourced from a “boot” capacitor
connected across the BOOT and PHASE pins. The boot
capacitor is charged from a 5V bias supply through a “boot
diode” each time the low-side MOSFET turns on, pulling the
PHASE pin low. The ISL6268 has an integrated boot diode
connected from the PVCC pin to the BOOT pin.
Diode Emulation
The ISL6268 normally operates in continuous conduction
mode (CCM), minimizing conduction losses by forcing the
low-side MOSFET to operate as a synchronous rectifier. An
DS(on)
DS(on)
Soft Start or Undervoltage
UG
LG
VCC below POR
MOSFET. The LG pull-down resistance is small in
MOSFET can be large. Adaptive shoot-through
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
Overvoltage
Overcurrent
t
LGFUGR
FIGURE 4. LG AND UG DEAD-TIME
50%
50%
8
PGOOD RESISTANCE
Undefined
t
95Ω
63Ω
32Ω
UGFLGR
GS(th)
at
ISL6268
improvement in light-load efficiency is achieved by allowing
the converter to operate in diode-emulation-mode (DEM),
where the low-side MOSFET behaves as a smart-diode,
forcing the device to block negative inductor current flow.
Positive-going inductor current flows from either the source
of the high-side MOSFET, or the drain of the low-side
MOSFET. Negative-going inductor current usually flows into
the drain of the low-side MOSFET. When the low-side
MOSFET conducts positive inductor current, the phase
voltage will be negative with respect to the GND and PGND
pins. Conversely, when the low-side MOSFET conducts
negative inductor current, the phase voltage will be positive
with respect to the GND and PGND pins. Negative inductor
current occurs when the output load current is less than half
the inductor ripple current. Sinking negative inductor through
the low-side MOSFET lowers efficiency through
unnecessary conduction losses. Efficiency can be further
improved with a reduction of unnecessary switching losses
by reducing the PWM frequency. It is characteristic of the R
architecture for the PWM frequency to decrease while in
diode emulation. The extent of the frequency reduction is
proportional to the reduction of load current. Upon entering
DEM, the PWM frequency makes an initial step-reduction
because of a 33% step-increase of the window voltage V
The converter will automatically enter DEM after the PHASE
pin has detected positive voltage, while the LG gate-driver
pin is high, for eight consecutive PWM pulses. The converter
will return to CCM on the following cycle after the PHASE pin
detects negative voltage, indicating that the body diode of
the low-side MOSFET is conducting positive inductor
current.
Overcurrent and Short Circuit Protection
The overcurrent protection (OCP) and short circuit protection
(SCP) setpoint is programmed with resistor R
connected across the ISEN and PHASE pins. The PHASE
pin is connected to the drain terminal of the low-side
MOSFET.
The SCP setpoint is internally set to twice the OCP setpoint.
When an OCP or SCP fault is detected, the PGOOD pin will
pull down to 32Ω and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V
below the falling POR threshold voltage
The OCP circuit does not directly detect the DC load current
leaving the converter. The OCP circuit detects the peak of
positive-flowing output inductor current. The low-side
MOSFET drain current I
positive output inductor current when the high-side MOSFET
is off. The inductor current develops a negative voltage
across the r
measured shortly after the LG gate-driver output goes high.
The ISEN pin sources the OCP sense current I
the OCP programming resistor R
0V with respect to the GND pin. The negative voltage across
DS(on)
of the low-side MOSFET that is
D
is assumed to be equal to the
ENTHF
SEN,
or if V
forcing the ISEN pin to
V
VCC_THF
CC
SEN
has decayed
SEN,
August 22, 2006
that is
.
through
FN6348.0
W
3
.